AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 11

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
Datasheet
PCIEXBAR – Flat memory-mapped address spaced to access device configuration
registers. This mechanism can be used to access PCI configuration space (0-FFh) and
Extended configuration space (100h-FFFh) for PCI Express devices. This enhanced
configuration access mechanism is defined in the PCI Express specification. (64MB,
128MB, or 256MB window).
DMIBAR –This window is used to access registers associated with the MCH/PCH Serial
Interconnect (DMI) register memory range. (4KB window)
GGCGMS – CPU UNCORE graphics control register, Graphics Mode Select. Used to
select the amount of main memory that is pre-allocated to support the internal
graphics device in VGA (non-linear) and Native (linear) modes. (0-64 MB options).
GGCGGMS – MCH graphics control register, GTT Graphics Memory Size. Used to select
the amount of main memory that is pre-allocated to support the Internal Graphics
Translation Table. ( (0-2 MB options).
Device 2, Function 0:
MMADR – IGD registers and internal graphics instruction port. (512KB window)
IOBAR – IO access window for internal graphics. Though this window address/data
register pair, using I/O semantics, the IGD and internal graphics instruction port
registers can be accessed. Note, this allows accessing the same registers as MMADR.
In addition, the IOBAR can be used to issue writes to the GTTADR table.
GMADR – Internal graphics translation window (128 MB, 256 MB or 512 MB window).
GTTADR – Internal graphics translation table location. (1MB window). Note that the
Base of GTT stolen Memory register (Device 0 A8) indicates the physical address base
which is 1MB aligned.
Device 2, Function 1:
MMADR – Function 1 IGD registers and internal graphics instruction port. (512KB
window)
The rules for the above programmable ranges are:
1. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or
2. In the case of overlapping ranges with memory, the memory decode will be given
There are NO Hardware Interlocks to prevent problems in the case of
overlapping ranges.
Accesses to overlapped ranges may produce indeterminate results.
Peer-to-peer cycles from DMI Interface to the Internal Graphics VGA
are not allowed.
Figure 1-1 represents system memory address map in a simplified form.
system designers' responsibility to limit memory population so that adequate PCI,
High BIOS, PCI Express Memory Mapped space, and APIC memory space can be
allocated.
priority.
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