AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 110

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.9.8
1.9.9
1.9.10
110
MLT2 - Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
HDR2 - Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains the Header Type of the IGD.
MMADR - Memory Mapped Range Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register requests allocation for the IGD registers and instruction ports. The
allocation is for 512 KB and the base address is defined by bits [31:19].
7:0
6:0
Bit
Bit
7
Acces
Access
RO
s
RO
RO
Default
Value
Default
00h
Value
00h
1b
Master Latency Timer Count Value (MLTCV):
Hardwired to 0s.
Multi Function Status (MFUNC):
Device. The Value of this register is determined
by Device #0, offset 54h, DEVEN[4]. If Device
#0 DEVEN[4] is set, the MFUNC bit is also set.
Header Code (H):
This is a 7-bit value that indicates the Header
Code for the IGD. This code has the value 00h,
indicating a type 0 configuration space format.
Indicates if the device is a Multi-Function
0/2/0/PCI
Dh
00h
8 bits
0/2/0/PCI
Eh
80h
8 bits
0/2/0/PCI
10-13h
00000000h
32 bits
RO;
RO;
RO; RW;
Processor Configuration Registers
Description
Description
Datasheet