AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 22

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2.6
1.2.7
1.2.7.1
22
Note: The Memory Map Base Register (MMADR) is used to access graphics control registers.
Note: DMI Interface is not allowed to access the SMM space.
Graphics Memory Address Ranges
The processor can be programmed to direct memory accesses to IGD when addresses
are within any of five ranges specified via registers in processor’s Device #2
configuration space.
The Graphics Memory Aperture Base Register (GMADR) is used to
access graphics memory allocated via the graphics translation table.
These ranges can reside above the Top-of-Low-DRAM and below High BIOS and APIC
address ranges. They MUST reside above the top of memory (TOLUD) and below 4 GB
so they do not steal any physical DRAM memory space.
GMADR is a Prefetchable range in order to apply USWC attribute (from the processor
point of view) to that range. The USWC attribute is used by the processor for write
combining.
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM
RAM). The IMC supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and
Top of Memory Segment (TSEG). System Management RAM space provides a memory
area that is available for the SMI handlers and code and data storage. This memory
resource is normally hidden from the system OS so that the processor has immediate
access to this memory space upon entry to SMM. IMC provides three SMRAM options:
•
•
•
The above 1 MB solutions require changes to compatible SMRAM handlers code to
properly execute above 1 MB.
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the CPU to
access SMM space. DRAM SMM space is defined as the range of physical DRAM
memory locations containing the SMM code. SMM space can be accessed at one of
three transaction address ranges: Compatible, High and TSEG. The Compatible and
TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space
is the same address range. Since the High SMM space is remapped the addressed and
DRAM SMM space is a different address range. Note that the High DRAM space is the
same as the Compatible Transaction Address space. The table below describes three
unique address ranges:
Below 1 MB option that supports compatible SMI handlers.
Above 1 MB option that allows new SMI handlers to execute with write-back
cacheable SMRAM.
Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. The TSEG area lies below IGD
stolen memory.
Processor Configuration Registers
Datasheet