AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 80
AU80610004392AAS LBLA
Manufacturer Part Number
AU80610004392AAS LBLA
Description
MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
Manufacturer
Intel
Series
ATOM - D500r
Datasheet
1.AU80610004392AAS_LBLA.pdf
(153 pages)
Specifications of AU80610004392AAS LBLA
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Operating Temperature Range
0°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1.6.15
80
C0ODTCTRL - Channel 0 ODT Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
ODT controls
31:12
11:8
7:4
3:0
Bit
Access
RW
RW
RW
RO
Default
00000h
Value
0000b
0000b
0000b
RST/
PWR
Core
Core
Core
Core
0/0/0/MCHBAR
29C-29Fh
00000000h
32 bits
RO; RW;
Reserved ()
DRAM ODT for Read Commands
(sd0_cr_odt_duration_rd):
Specifies the duration in MDCLKs to assert
DRAM ODT for Read Commands. The Async
value should be used when the Dynamic
Powerdown bit is set. Else use the Sync value.
DRAM ODT for Write Commands
(sd0_cr_odt_duration_wr):
Specifies the duration in MDCLKs to assert
DRAM ODT for Write Commands. The Async
value should be used when the Dynamic
Powerdown bit is set. Else use the Sync value.
MCH ODT for Read Commands
(sd0_cr_mchodt_duration):
Specifies the duration in MDCLKs to assert MCH
ODT for Read Commands
Processor Configuration Registers
Description
Datasheet
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