AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 126

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.9.34
126
GDRST - Graphics Debug Reset
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
7:4
3:2
Bit
1
0
Access
RW
RW
RO
RO
Default
Value
00b
0h
0b
0b
Reserved ():
Graphics Reset Domain (GRDOM):
Graphics Reset Domain
00 – Full Graphics Reset will be performed
(both render and display clock domain resets
asserted
01 – Reserved (Illegal Programming)
10 – Reserved (Illegal Programming)
11 – Reserved (Illegal Programming)
Reserved ():
Graphics Reset Enable (GR):
Setting this bit asserts graphics-only reset. The
clock domains to be reset are determined by
GRDOM. Hardware resets this bit when the
reset is complete. Setting this bit without
waiting for it to clear, is undefined behavior.
Once this bit is set to a "1" all GFX core MMIO
registers are returned to power on default
state. All Ring buffer pointers are reset,
command stream fetches are dropped and
ongoing render pipeline processing is halted,
state machines and State Variables returned to
power on default state. If the Display is reset,
all display engines are halted (garbage on
screen). VGA memory is not available, Store
DWORDs and interrupts are not guaranteed to
be completed. Device #2 IO registers are not
available.
Device #2 Config registers continue to be
available while Graphics reset is asserted.
This bit is HW auto-clear.
0/2/0/PCI
C0h
00h
8 bits
RO; RW;
Processor Configuration Registers
Description
Datasheet