AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 123

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.9.29
1.9.30
Datasheet
SCWBFC - Secondary CWB Flush Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
A CPU Dword/Qword write to this space flushes the Secondary CWB/DWB of all writes.
The data is discarded. A CPU read to this space may result in a system hang.
This register is for hardware debug purposes only. This is not relevant for software.
All the data stored in the secondary CWB is flushed to memory before a write to this
page is completed on the Front side bus. The write data is discarded.
All transactions from the CPU that follow are not processed by the chipset till the
"flush write" completes creating a fence beyond which coherency is guaranteed.
A read to this page does not flush the primary CWB/DWB and returns Zeros.
MSI_CAPID - Message Signaled Interrupts Capability ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
When a device supports MSI it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address. The
reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0]
@ 7Fh). In that case walking this linked list will skip this capability and instead go
directly to the PCI PM capability.
63:0
15:8
7:0
Bit
Bit
Access
Access
RO
RO
W
00000000
00000000
Default
Default
Value
Value
D0h
05h
h
Secondary CWB Flush Control (SCWBFC):
A CPU Dword/Qword write to this space flushes
the Secondary CWB/DWB of all writes. The data
is discarded. A CPU read to this space may
result in a system hang.
Pointer to Next Capability (POINTNEXT):
capabilities list which is the Power Management
capability.
Capability ID (CAPID):
(capability structure) as being for MSI registers.
This contains a pointer to the next item in the
Value of 05h identifies this linked list item
0/2/0/PCI
68-6Fh
0000000000000000h
64 bits
0/2/0/PCI
90-91h
D005h
16 bits
W;
RO;
Description
Description
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