AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 68

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.6.2
68
C0DRB0 - Channel 0 DRAM Rank Boundary Address 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The DRAM Rank Boundary Registers define the upper boundary address of each DRAM
rank with a granularity of 64MB. Each rank has its own single-word DRB register.
These registers are used to determine which chip select will be active for a given
address. Channel and rank map:
Programming guide:
1. Non-stacked mode:
2. Stacked mode:
15:10
9:0
Bit
ch0 rank0: 200h
ch0 rank1: 202h
ch0 rank2: 204h
ch0 rank3: 206h
If Channel 0 is empty, all of the C0DRBs are programmed with 00h.
C0DRB0 = Total memory in ch0 rank0 (in 64MB increments)
C0DRB1 = Total memory in ch0 rank0 + ch0 rank1 (in 64MB increments)
and so on.
CODRBs:
Similar to Non-stacked mode.
Access
RW/L
RO
000000b
Default
Value
000h
RST/
PWR
Core
Core
0/0/0/MCHBAR
200-201h
0000h
16 bits
RW/L; RO;
Reserved ():
Channel 0 Dram Rank Boundary Address 0
(C0DRBA0):
This register defines the DRAM rank boundary
for rank0 of Channel 0 (64 MB granularity)
=R0
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
Processor Configuration Registers
Description
Datasheet