AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 70

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.6.5
1.6.6
70
C0DRB3 - Channel 0 DRAM Rank Boundary Address 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
See C0DRB0
C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
15:10
9:0
Bit
Ch0 Rank0, 1:
Ch0 Rank2, 3:
Access
RW/L
RO
000000b
Default
Value
000h
208h-209h
20Ah-20Bh
RST/
PWR
Core
Core
0/0/0/MCHBAR
206-207h
0000h
16 bits
0/0/0/MCHBAR
208-209h
0000h
16 bits
RW/L; RO;
RW/L;
Reserved ():
Channel 0 DRAM Rank Boundary Address 3
(C0DRBA3):
This register defines the DRAM rank boundary
for rank3 of Channel 0 (64 MB granularity)
=(R3 + R2 + R1 + R0)
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
Processor Configuration Registers
Description
Datasheet