AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 24

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2.7.4
1.2.7.5
1.2.7.6
1.2.7.7
24
Table 1-6. SMM Control Table
SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit
allows software to write to the SMM ranges without being in SMM mode. BIOS
software can use this bit to initialize SMM code at power up. The D_LCK bit limits the
SMM range access to only SMM mode accesses. The D_CLS bit causes SMM data
accesses to be forwarded to the DMI Interface. The SMM software can use this bit to
write to video memory while running SMM code out of DRAM.
SMM Space Decode and Transaction Handling
Only the CPU is allowed to access SMM space. DMI Interface originated transactions
are not allowed to SMM space. The following tables indicate the action taken by the
IMC when the accesses to the various enabled SMM space occurs.
CPU WB Transaction to an Enabled SMM Address Space
CPU Writeback transactions (REQa[1]# = 0) to enabled SMM Address Space must be
written to the associated SMM DRAM even though D_OPEN=0 and the transaction is
not performed in SMM mode. This ensures SMM space cache coherency when
cacheable extended SMM space is used.
SMM Access through GTT TLB
Accesses through GTT TLB address translation to enabled SMM DRAM space are not
allowed. Writes will be routed to Memory address 000C_0000h with byte enables de-
asserted and reads will be routed to Memory address 000C_0000h. If a GTT TLB
G_SMRAME
G_SMRAME
Enable
Global
1.
0
1
1
1
1
1
1
1
1
1
D_LCK
H_SMRAM_EN
x
0
0
0
0
0
1
1
1
High Enable
1
D_CLS
X
X
X
0
0
1
1
0
1
D_OPEN
TSEG_EN
x
0
0
1
0
1
x
x
x
Enable
TSEG
1
Processor Configuration Registers
CPU in
Mode
SMM
x
0
1
x
1
x
0
1
1
Compatible
(C) Range
Disabled
Access
Disable
Disable
Disable
Enable
Enable
Enable
Invalid
Enable
Enable
Code
SMM
Range
Enable
High
(H)
Access
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Invalid
Enable
SMM
Data
Datasheet
Range
Enable
TSEG
(T)