AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 144
AU80610004392AAS LBLA
Manufacturer Part Number
AU80610004392AAS LBLA
Description
MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
Manufacturer
Intel
Series
ATOM - D500r
Datasheet
1.AU80610004392AAS_LBLA.pdf
(153 pages)
Specifications of AU80610004392AAS LBLA
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Operating Temperature Range
0°C To +100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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144
7:4
3:2
Bit
1
0
Access
RO
RO
RO
RO
Default
Value
0011b
00b
0b
0b
NOTE: This register is locked and becomes
NOTE: This register is locked and becomes
Internal Graphics Translation Table. The BIOS
ensures that memory is pre-allocated only when
Internal graphics is enabled.
00: No memory pre-allocated. GTT cycles
(Mem and IO) are not claimed.
01: 1 MB of memory pre-allocated for GTT.
10: Reserved
11: Reserved
Graphics Mode Select (GMS):
This field is used to select the amount of Main
Memory that is pre-allocated to support the
Internal Graphics device in VGA (non-linear)
and Native (linear) modes. The BIOS ensures
that memory is pre-allocated only when Internal
graphics is enabled.
0000:
(IGD) does not claim VGA cycles (Mem and IO),
and the Sub-Class Code field within Device 2
function 0 Class Code register is 80.
0001:
pre-allocated for frame buffer.
0011:
pre-allocated for frame buffer.
BIOS Requirement: BIOS must not set this field
to 000 if IVD (bit 1 of this register) is 0.
Reserved ()
IGD VGA Disable (IVD):
0: Enable. Device 2 (IGD) claims VGA memory
and IO cycles, the Sub-Class Code within Device
2 Class Code register is 00.
1: Disable. Device 2 (IGD) does not claim VGA
cycles (Mem and IO), and the Sub- Class Code
field within Device 2 function 0 Class Code
register is 80.
BIOS Requirement: BIOS must not set this bit
to 0 if the GMS field (bits 6:4 of this register)
pre-allocates no memory.
This bit MUST be set to 1 if Device 2 is disabled.
Reserved ():
Read Only when the D_LCK bit in the
SMRAM register is set.
Read Only when the D_LCK bit in the
SMRAM register is set.
No memory pre-allocated. Device 2
DVMT (UMA) mode, 1 MB of memory
DVMT (UMA) mode, 8 MB of memory
Processor Configuration Registers
Description
Datasheet
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