AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 42

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.16
42
PCIEXBAR - PCI Express Register Range Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the PCI Express configuration space. This window of
addresses contains the 4KB of configuration space for each PCI Express device that
can potentially be part of the PCI Express Hierarchy associated with the CPU Uncore.
There is not actual physical memory within this window of up to 256MB that can be
addressed. The actual length is determined by a field in this register. Each PCI
Express Hierarchy requires a PCI Express BASE register. The CPU Uncore supports one
PCI Express hierarchy. The region reserved by this register does not alias to any PCI
2.3 compliant memory mapped space. For example MCHBAR reserves a 16KB space
and CHAPADR reserves a 4KB space both outside of PCIEXBAR space. They cannot be
overlaid on the space reserved by PCIEXBAR for devices 0 and 7 respectively.
On reset, this register is disabled and must be enabled by writing a 1 to the enable
field in this register. This base address shall be assigned on a boundary consistent
with the number of buses (defined by the Length field in this register), above TOLUD
and still within 64 bit addressable memory space. All other bits not decoded are read
only 0. The PCI Express Base Address cannot be less than the maximum address
written to the Top of physical memory register (TOLUD). Software must guarantee
that these ranges do not overlap with known ranges located above TOLUD. Software
must ensure that the sum of Length of enhanced configuration region + TOLUD +
(other known ranges reserved above TOLUD) is not greater than the 64-bit
addressable limit of 64GB. In general system implementation and number of PCI/PCI
express/PCI-X buses supported in the hierarchy will dictate the length of the region.
63:36
35:28
Bit
Access
RW/L
RO
0000000h
Default
Value
0Eh
RST/
PWR
Core
Core
0/0/0/PCI
60-67h
00000000E0000000h
64 bits
RW/L; RW/L/K; RO;
PCI Express Base Address + Bus Number * 1MB
+ Device Number * 32KB + Function Number *
4KB
Reserved (PCIEXBAR_rsv):
PCI Express Base Address (PCIEXBAR):
This field corresponds to bits 35 to 28 of the
base address for PCI Express enhanced
configuration space. BIOS will program this
register resulting in a base address for a
contiguous memory address space; size is
defined by bits 2:1 of this register.
This Base address shall be assigned on a
boundary consistent with the number of buses
(defined by the Length field in this register)
above TOLUD and still within 64-bit addressable
memory space. The address bits decoded
depend on the length of the region defined by
this register.
The address used to access the PCI Express
configuration space for a specific device can be
determined as follows.
Processor Configuration Registers
Description
Datasheet