AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 135

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.10.4
Datasheet
PCISTS2 - PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant
master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL#
timing that has been set by the IGD.
10:9
Bit
15
14
13
12
11
8
7
6
5
4
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
1b
0b
0b
1b
Detected Parity Error (DPE):
Since the IGD does not detect parity, this bit is
always hardwired to 0.
Signaled System Error (SSE):
is hardwired to 0.
Received Master Abort Status (RMAS):
this bit is hardwired to 0.
Received Target Abort Status (RTAS):
this bit is hardwired to 0.
Signaled Target Abort Status (STAS):
abort semantics.
DEVSEL Timing (DEVT):
Master Data Parity Error Detected (DPD):
disabled (and the IGD does not do any parity
detection), this bit is hardwired to 0.
Fast Back-to-Back (FB2B):
back when the transactions are not to the same
agent.
User Defined Format (UDF):
66 MHz PCI Capable (66C):
Capability List (CLIST):
The IGD never asserts SERR#, therefore this bit
The IGD never gets a Master Abort, therefore
The IGD never gets a Target Abort, therefore
Hardwired to 0. The IGD does not use target
N/A. These bits are hardwired to "00".
Since Parity Error Response is hardwired to
Hardwired to 1. The IGD accepts fast back-to-
Hardwired to 0.
N/A - Hardwired to 0.
This bit is set to 1 to indicate that the register
0/2/1/PCI
6-7h
0090h
16 bits
RO;
Description
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