CY8C3866AXI-040 Cypress Semiconductor Corp, CY8C3866AXI-040 Datasheet - Page 87

PSOC 3 TQFP

CY8C3866AXI-040

Manufacturer Part Number
CY8C3866AXI-040
Description
PSOC 3 TQFP
Manufacturer
Cypress Semiconductor Corp
Series
PSOC™ 3 CY8C38xxr
Datasheet

Specifications of CY8C3866AXI-040

Package / Case
*
Voltage - Supply (vcc/vdd)
1.71 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
67MHz
Number Of I /o
62
Eeprom Size
2K x 8
Core Processor
8051
Program Memory Type
FLASH
Ram Size
8K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 2x20b, D/A 4x8b
Oscillator Type
Internal
Peripherals
CapSense, DMA, LCD, POR, PWM, WDT
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB
Core Size
8-Bit
Processor Series
CY8C38
Core
8051
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART, USB
Maximum Clock Frequency
67 MHz
Number Of Programmable I/os
28 to 72
Number Of Timers
4
Operating Supply Voltage
0.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Controller Family/series
(8051) PSOC 3
No. Of I/o's
62
Eeprom Memory Size
2KB
Ram Memory Size
8KB
Cpu Speed
67MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Figure 11-37. Delta-sigma ADC DNL vs Output Code, 16-bit,
48 ksps, 25 °C V
11.2.3 Voltage Reference
Table 11-27. Voltage Reference Specifications
See also ADC external reference specifications in Section 11.2.2.
11.2.4 Analog Globals
Table 11-28. Analog Globals Specifications
11.2.5 Comparator
Table 11-29. Comparator DC Specifications
Document Number: 001-11729 Rev. *R
Notes
V
Rppag
Rppmuxbus
V
V
V
V
Parameter
39. Based on device characterization (Not production tested).
40. The resistance of the analog global and analog mux bus is high if V
41. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM.
REF
OS
OS
OS
HYST
Parameter
Parameter
mux bus under these conditions is not recommended.
Precision reference voltage
Temperature drift
Long term drift
Thermal cycling drift (stability)
Resistance pin-to-pin through
analog global
Resistance pin-to-pin through
analog mux bus
Input offset voltage in fast mode
Input offset voltage in slow mode
Input offset voltage in fast mode
Input offset voltage in slow mode
Input offset voltage in ultra
low-power mode
Hysteresis
DDA
= 3.3 V
Description
Description
Description
[40]
[39]
[40]
[39]
[41]
[41]
V
V
Factory trim, Vdda > 2.7 V,
Vin ≥ 0.5 V
Factory trim, Vin ≥ 0.5 V
Custom trim
Custom trim
Hysteresis enable mode
Initial trimming
DDA
DDA
DDA
= 3.0 V
= 3.0 V
≤ 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog
Conditions
Conditions
Conditions
Figure 11-38. Delta-sigma ADC INL vs Output Code, 16-bit,
48 ksps, 25 °C V
DDA
PSoC
(–0.1%)
= 3.3 V
1.023
Min
Min
Min
®
1.024
Typ
100
100
3: CY8C38 Family
Typ
±12
Typ
939
721
10
(+0.1%)
1.025
Max
Max
20
1461
1135
Max
10
32
Data Sheet
9
4
4
Page 87 of 129
ppm/Khr
ppm/°C
Units
Units
ppm
Units
mV
mV
mV
mV
mV
mV
V
Ω
Ω
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