CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 116
CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
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1.10.1
116
TSC1 - Thermal Sensor Control 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
This register controls the operation of the internal thermal sensor located in the
graphics region of the die.
15:14
13:10
9:9
7:1
Bit
8
Access
RS-WC
RW
RO
RO
RO
Default
Value
00b
00h
0h
0h
0b
Reserved
Digital Hysteresis Amount (DHA)
This bit enables the analog hysteresis control to the thermal
sensor. When enabled, about 1 degree of hysteresis is
applied. This bit should normally be off in thermometer mode
since the thermometer mode of the thermal sensor defeats
the usefulness of analog hysteresis.
0 = hysteresis disabled
1 = analog hysteresis enabled.
This setting falls within the same byte as the In Use bit in bit
8. Therefore if this setting is read, software must write a 1 to
bit 8 if it does not intend to maintain ownership of the
Thermal Sensor resource.
Reserved
In Use (IU)
Software semaphore bit. After a full processor RESET, a read
to this bit returns a 0. After the first read, subsequent reads
will return a 1.
Writing a 1 to this bit will reset the next read value to 0.
Writing a 0 to this bit has no effect.
Software can poll this bit until it reads a 0, and will then own
the usage of the thermal sensor. This bit has no other effect
on the hardware, and is only used as a semaphore among
various independent software threads that may need to use
the thermal sensor.
Software that reads this register but does not intend to claim
exclusive access of the thermal sensor must write a one to
this bit if it reads a 0, in order to allow other software threads
to claim it.
See also THERM Bit 15, which is an independent additional
semaphore bit.
Reserved
0/0/0/MCHBAR
1001-1002h
0000h
RW-L; RO; RW; RS-WC
16 bits
0h
(Sheet 1 of 2)
Description
Processor Configuration Registers
Datasheet
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