CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 30
CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
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1.2.3.1.2
30
Figure 6.
Case #2: Greater than 4 GB of Physical Memory
Greater than 4 GB of Physical Memory
In this case, the amount of memory remapped is the range between TOLUD and 4 GB.
This physical memory is mapped to the logical address range defined between the
REMAPBASE and the REMAPLIMIT registers.
Example: 5 GB of Physical Memory, with 1 GB allocated to Memory Mapped IO:
•
•
•
•
•
Populated Physical Memory = 5 GB
Address Space allocated to memory mapped IO = 1 GB
Remapped Physical Memory = 1G B
TOM – 050h (5 GB)
Intel ME stolen size – 00000b (0 MB)
TOUUD BASE
RECLAIM BASE + x
RECLAIM LIMIT =
RECLAIM BASE
64MB aligned
TOLUD BASE
64MB aligned
HOST/SYSTEM VIEW
64MB aligned
64G
0
MEMORY
PCI MMIO
RECLAIM
REGION
HMMIO
ABOVE
DRAM”
DRAM
TSEG
“LOW
4 GB
X
4G
GFX Stolen BASE
GFX GTT Stolen BASE
EP Stolen BASE
(DRAM CONTROLLER VIEW)
Processor Configuration Registers
TSEG BASE
TOM
PHYSICAL MEMORY
0
(0-256 MB)
INVISIBLE
RECLAIM
GFX GTT
(0-64 MB)
(1-64MB)
EP-UMA
STOLEN
(0-8 MB)
VISIBLE
VISIBLE
Wasted
>4 GB
TSEG
< 4GB
0MB -
63MB
GFX
OS
OS
OS
64MB aligned
64MB aligned
1MB aligned
1MB aligned
64MB aligned for reclaim
1MB aligned
1MB aligned
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