CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 85

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.9.6
1.9.7
Datasheet
C0DRB3 - Channel 0 DRAM Rank Boundary Address 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
See C0DRB0.
C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
DRA[7:0] = “00” means cfg0, DRA[7:0] =”01” means cfg1.... DRA[7:0] = “09” means
cfg9 and so on.
15:10
9:0
Bit
Ch0 Rank 0, 1: 208h-209h
Ch0 Rank 2, 3: 20Ah-20Bh
Ch1 Rank 0, 1: 608h - 609h
Ch1 Rank 2, 3: 60Ah - 60Bh
Access
RW-L
RO
Default
Value
000h
00h
Reserved
Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3)
This register defines the DRAM rank boundary for Rank 3 of
Channel 0 (64 MB granularity) = (R3 + R2 + R1 + R0)
R0 = Total Rank 0 memory size/64 MB
R1 = Total Rank 1 memory size/64 MB
R2 = Total Rank 2 memory size/64 MB
R3 = Total Rank 3 memory size/64 MB
This register is locked by Intel ME stolen Memory lock.
0/0/0/MCHBAR
206-207h
0000h
RO; RW-L
16 bits
0/0/0/MCHBAR
208-209h
0000h
RW-L
16 bits
Description
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