CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 169

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
Bit
3
2
1
0
Access
RW
RW
RW
RW
Default
Value
0b
0b
0b
0b
VGA Enable (VGAEN)
Controls the routing of CPU initiated transactions targeting
VGA compatible I/O and memory address ranges. See the
VGAEN/MDAP table in device 0, offset 97h[0].
The VGA enable bit must only be set if there exists a VGA
device within the PCI express hierarchy on the secondary side
of the bridge. It must not be set if no such device is
discovered during PCI enumeration.
ISA Enable (ISAEN)
Needed to exclude legacy resource decode to route ISA
resources to legacy decode path. Modifies the response by
the processor to an I/O access issued by the CPU that target
ISA I/O addresses. This applies only to I/O addresses that are
enabled by the IOBASE and IOLIMIT registers.
0 = All addresses defined by the IOBASE and IOLIMIT for CPU
1 = Processor will not forward to PCI Express-G any I/O
SERR Enable (SERREN)
0 = No forwarding of error messages from secondary side to
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages
Parity Error Response Enable (PEREN)
Controls whether or not the Master Data Parity Error bit in the
Secondary Status register is set when the PROCESSOR
receives across the link (upstream) a Read Data Completion
Poisoned TLP
0 = Master Data Parity Error bit in Secondary Status register
1 = Master Data Parity Error bit in Secondary Status register
I/O transactions is mapped to PCI Express-G.
transactions addressing the last 768 bytes in each 1-KB
block even if the addresses are within the range defined
by the IOBASE and IOLIMIT registers.
primary side that could result in an SERR.
result in SERR message when individually enabled by the
Root Control register.
CANNOT be set.
CAN be set.
(Sheet 2 of 2)
Description
169