CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 276

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.18.12
1.18.13
276
FEUADDR_REG - Fault Event Upper Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the interrupt message address. For platforms supporting only
interrupt messages in the 32-bit address range, this register is treated as read-only
(0).
AFLOG_REG - Advanced Fault Log Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to specify the base address of memory-resident fault-log region.This register
is treated as read-only (0) for implementations not supporting advanced translation
fault logging (AFL field reported as 0 in the Capability register). This register is sticky
and can be cleared only through powergood reset or via software clearing the RW1C
fields by writing a 1.
63:12
31:0
Bit
Bit
Access
Access
RO
RO
00000000
00000000h
Default
00000h
Value
Default
Value
Fault Log Address (FLA)
This field specifies the base of size-aligned fault-log region in
system memory. Hardware may ignore and not implement
Bits 63:HAW, where HAW is the host address width.
Software specifies the base address and size of the fault log
region through this register, and programs it in hardware
through the SFL field in the Global Command register.
When implemented, reads of this field returns value that was
last programmed to it.
Message Upper Address (MUA)
This register need to be implemented only if hardware
supports 64-bit message address. If implemented, the
contents of this register specify the upper 32-bits of a 64-
bit MSI write transaction. If hardware does not support 64-
bit messages, the register is treated as read-only (0).
0/0/0/VC0PREMAP
44-47h
00000000h
RO
32 bit
0/0/0/VC0PREMAP
58-5Fh
0000000000000000h
RO
64 bits
(Sheet 1 of 2)
Processor Configuration Registers
Description
Description
Datasheet