CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 232

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.16.11
232
GMADR - Graphics Memory Range Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
IGD graphics memory base address is specified in this register.
Software must not change the value in MSAC[2:1] (offset 62h) after writing to the
GMADR register.
63:36
35:22
63:36
35:29
21:4
2:1
Bit
Bit
3
0
Access
Access
RW
RW
RW
RW
RO
RO
RO
RO
0000000h
0000000b
0000000h
Default
Default
Value
00000h
0000h
Value
10b
0b
0b
FLR, Core
FLR, Core
FLR, Core
FLR, Core
RST/
PWR
RST/
PWR
Core
Core
Core
Core
0/2/0/PCI
18-1Fh
000000000000000Ch
RO; RW-L; RW
64 bits
(Sheet 1 of 2)
Memory Base Address (MBA2)
Set by the OS, these bits correspond to address
signals [63:36].
Memory Base Address (MBA)
Set by the OS, these bits correspond to address
signals [35:29].
Reserved for Memory Base Address
Must be set to 0 since addressing above 64 GB
is not supported.
Memory Base Address (MBA)
Set by the OS, these bits correspond to address
signals [35:22]. 4 MB combined for MMIO and
Global GTT table aperture (512 KB for MMIO
and 2 MB for GTT).
Reserved
Hardwired to 0's to indicate at least 4-MB
address range.
Prefetchable Memory (PREFMEM)
Hardwired to 0 to prevent prefetching.
Memory Type (MEMTYP)
00: To indicate 32-bit base address
01: Reserved
10: To indicate 64 bit base address
11: Reserved
Memory/IO Space (MIOS)
hard wired to 0 to indicate memory space.
Processor Configuration Registers
Description
Description
Datasheet