CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 74

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.8.28
74
ERRSTS - Error Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
This register is used to report various error conditions via the SERR DMI messaging
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked by
clearing the appropriate status bit by software writing a 1 to it.
15:13
6:2
Bit
12
11
10
9
8
7
1
0
Access
RWC-S
RWC-S
RWC-S
RWC-S
RWC-S
RWC-S
RO
RO
RO
RO
Default
Value
000b
00h
0b
0b
0b
0b
0b
0b
0b
0b
Reserved
Device 2 Software Generated Event for SMI
(GSGESMI)
This indicates the source of the SMI was a Device 2 Software
Event.
Memory Controller Thermal Sensor Event for SMI/
SCI/SERR (GTSE)
Indicates that a Memory controller Thermal Sensor trip has
occurred and an SMI, SCI or SERR has been generated. The
status bit is set only if a message is sent based on thermal
event enables in Error command, SMI command and SCI
command registers. A trip point can generate one of SMI,
SCI, or SERR interrupts (two or more per event is illegal).
Multiple trip points can generate the same interrupt, if
software chooses this mode, subsequent trips may be lost. If
this bit is already set, then an interrupt message will not be
sent on a new thermal sensor event.
Reserved
LOCK to non-DRAM Memory Flag (LCKF)
When this bit is set to 1, the memory controller has detected
a lock operation to memory space that did not map into
DRAM.
Reserved
DRAM Throttle Flag (DTF)
0 = Software has cleared this flag since the most recent
1 = Indicates that a DRAM Throttling condition occurred.
Reserved
Reserved
Reserved
0/0/0/PCI
C8-C9h
0000h
RO; RWC-S
16 bits
0h
throttling event.
Processor Configuration Registers
Description
Datasheet