CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 164

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.18
164
Note:
PMLIMIT1 - Prefetchable Memory Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register in conjunction with the corresponding Upper Limit Address register
controls the CPU to PCI Express-G prefetchable memory access routing based on the
following formula:
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range is at the top of a 1-MB aligned memory block.
Prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e., prefetchable) from the CPU perspective.
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
15:4
15:4
3:0
Bit
3:0
Bit
Access
Access
RW
RO
RW
RO
Default
Default
Value
Value
000h
FFFh
1h
1h
Prefetchable Memory Address Limit (PMLIMIT)
Corresponds to A[31:20] of the upper limit of the address
range passed to PCI Express-G.
64-bit Address Support (RSVD)
Indicates that the upper 32 bits of the prefetchable memory
region limit address are contained in the Prefetchable
Memory Base Limit Address register at 2Ch
Prefetchable Memory Base Address (MBASE)
Corresponds to A[31:20] of the lower limit of the memory
range that is passed to PCI Express-G.
64-bit Address Support (64-bit Address Support)
Indicates that the upper 32 bits of the prefetchable memory
region base address are contained in the Prefetchable
Memory base Upper Address register at 28h.
0/1/0/PCI
26-27h
0001h
RO; RW
16 bits
Description
Processor Configuration Registers
Description
Datasheet