CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 49

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.8.3
Datasheet
PCICMD - PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Since processor Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
15:10
Bit
9
8
7
Access
RW
RO
RO
RO
Default
Value
00h
0b
0b
0b
Reserved
Fast Back-to-Back Enable (FB2B)
This bit controls whether or not the master can do fast
back-to-back write. Since device 0 is strictly a target this
bit is not implemented and is hard wired to 0. Writes to this
bit position have no effect.
SERR Enable (SERRE)
This bit is a global enable bit for Device 0 SERR messaging.
The processor does not have an SERR signal. The
processor communicates the SERR condition by sending an
SERR message over DMI to the PCH.
0 = The SERR message is not generated by the processor
1 = The processor is enabled to generate SERR messages
This bit only controls SERR messaging for Device 0. Device
1 has its own SERRE bits to control error reporting for error
conditions occurring in that device. The control bits are
used in a logical OR manner to enable the SERR DMI
message mechanism.
Address/Data Stepping Enable (ADSTEP) Address/
data stepping is not implemented in the processor, and this
bit is hard wired to 0. Writes to this bit position have no
effect.
0/0/0/PCI
4-5h
0006h
RO; RW
16 bits
Encoding
(Sheet 1 of 2)
for Device 0.
over DMI for specific Device 0 error conditions that are
individually enabled in the ERRCMD and DMIUEMSK
registers. The error status is reported in the ERRSTS,
PCISTS, and DMIUEST registers.
0b
1b
Device 0 SERR disabled
Device 0 SERR enabled
Description
Description
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