CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 70

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.8.23
70
BGSM - Base of GTT Stolen Memory
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains the base address of graphics data stolen DRAM memory. BIOS
determines the base of graphics data stolen memory by subtracting the graphics data
stolen memory size (PCI Device 0 Offset 52 Bits 7:4) from where TOLUD (PCI Device 0
Offset B0 Bits 15:04) would be if there were no memory reserved for TSEG, internal
graphics, or the GTT for internal graphics.
This register is locked and becomes Read Only when CMD.LOCK. MEMCONFIG is
received or when ME_SM_LOCK is set to 1.
31:20
19:0
Bit
Access
RW-L
RO
Default
00000h
Value
000h
Graphics Base of Stolen Memory (GBSM)
This register contains Bits 31:20 of the base address of
stolen DRAM memory. BIOS determines the base of graphics
stolen memory by subtracting the graphics stolen memory
size (PCI Device 0 Offset 52 Bits 9:8) from the graphics
stolen memory base (PCI Device 0 Offset A4 Bits 31:20).
Reserved
0/0/0/PCI
A8-ABh
00000000h
RW-L; RO
32 bits
Processor Configuration Registers
Description
Datasheet