CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 162

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.15
1.13.16
162
MBASE1 - Memory Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express-G non-prefetchable memory access
routing based on the following formula:
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be 0.
Thus, the bottom of the defined memory address range is aligned to a 1-MB boundary.
MLIMIT1 - Memory Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express-G non-prefetchable memory access
routing based on the following formula:
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
MEMORY_BASE=< address =<MEMORY_LIMIT
MEMORY_BASE=< address =<MEMORY_LIMIT
15:4
3:0
4:0
Bit
Bit
5
Access
Access
RO
RO
RW
RO
Default
Default
Value
Value
00h
FFFh
0b
0h
66-/60-MHz Capability (CAP66)
Not Applicable or Implemented. Hard wired to 0.
Reserved
Memory Address Base (MBASE)
Corresponds to A[31:20] of the lower limit of the memory
range that is passed to PCI Express-G.
Reserved
0/1/0/PCI
20-21h
FFF0h
RO; RW
16 bits
0/1/0/PCI
22-23h
0000h
RO; RW
16 bits
(Sheet 2 of 2)
Processor Configuration Registers
Description
Description
Datasheet