CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 28

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.2.3.1
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Programming Model
The memory boundaries of interest are:
Determine the following Mapping steps:
The following diagrams show the four possible general cases of remapping.
1. TOM
2. TOM minus Intel ME stolen size
3. MMIO allocation
4. TOLUD
5. GFX stolen base
6. GFX GTT stolen base
7. TSEG base
8. Remap base/limit
9. TOUUD
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Bottom of logical address remap window defined by the REMAPBASE register, which
is calculated and loaded by BIOS.
Top of logical address remap window defined by the REMAPLIMIT register, which is
calculated and loaded by BIOS.
Bottom of physical remap memory defined by the existing TOLUD register.
Top of physical remap memory, which is implicitly defined by either 4 GB or TOM
minus Manageability Engine stolen size.
Case #1: Less than 4 GB of Physical Memory, no remap
Case #2: Greater than 4 GB of Physical Memory
Case #3: 4 GB or Less of Physical Memory
Case #4: Greater than 4 GB of Physical Memory, remap
Processor Configuration Registers
Datasheet