CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 298
CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
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1.18.33
298
PEGVTCMPLRESR - PEG VT-d Completion Resource
Dedication
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register provides a programmable interface to dedicate the PEG0 and Completion
Tracking Queue resources to PEG0 VC0 read, PEG0 VC0 writes VT-d fetch.
31:30
29:25
24:20
19:15
14:10
9:5
Bit
Access
RW-L
RW-L
RW-L
RW-L
RO
RO
Default
10000b
00000b
00000b
10000b
00000b
Value
00b
PEG Completion Tracking Queue Resource Sharing
Mode (PCTQRSM)
11: Intel Reserved
01: Intel Reserved
00: PEG0 is assigned all of the resources in the Completion
Tracking Queue.
Intel Reserved
Intel Reserved
Intel Reserved
PEG0 VT-d Completion Tracking Queue Resource
Available (PEG0VTCTRA)
Number of entries available in PEG0 VT-d Completion
Tracking Queue. 1-based. The values programmed in the
fields below must not be greater than the value advertised in
this field.
PEG0 VC0 Write VT-d Completion Tracking Queue
Resource Threshold (PEG0VC0WRCTQRT)
1-based minimum threshold value used to throttle PEG0 VC0
Write VT-d fetch. When the number of free PEG0 VT-d
Completion Tracking Queue entries equals or falls below the
value programmed in this field, PEG0 VC0 Write VT-d fetch is
throttled until the number of free PEG0 Completion Tracking
Queue entries rise above this threshold.
For example:
00000 – Throttle PEG0 VC0 Write VT-d Fetch when there is
no entry left.
00001 – Throttle PEG0 VC0 Write VT-d Fetch when there is 1
or less entry left.
00010 - Throttle PEG0 VC0 Write VT-d Fetch when there are
2 or less entry left.
00011 – Throttle PEG0 VC0 Write VT-d Fetch when there are
3 or less entry left.
00100 - Throttle PEG0 VC0 Write VT-d Fetch when there are
4 or less entry left.
0/0/0/VC0PREMAP
F08-F0Bh
20004000h
RW-L; RO
32 bits
(Sheet 1 of 2)
Processor Configuration Registers
Description
Datasheet
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