CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 77

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.8.31
1.8.32
Datasheet
SCICMD - SCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively. Note that one and only one message type can be enabled.
SKPD - Scratchpad Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register holds 32 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
15:12
10:2
31:0
Bit
Bit
11
1
0
Access
Access
RW
RW
RW
RW
RO
RO
00000000h Scratchpad Data (SKPD)
Default
Default
Value
Value
000h
0h
0b
0b
0b
1 DWORD of data storage.
Reserved
SCI on Processor Thermal Sensor Trip (TSTSCI)
0 = Reporting of this condition via SCI messaging is
1 = A SCI DMI special cycle is generated by processor
Reserved
Reserved
Reserved
0/0/0/PCI
CE-CFh
0000h
RO; RW
16 bits
0/0/0/PCI
DC-DFh
00000000h
RW
32 bits
disabled.
when the thermal sensor trip requires an SCI. A
thermal sensor trip point cannot generate more than
one special cycle.
Description
Description
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