CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 227

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
10:9
2:0
Bit
12
11
8
7
6
5
4
3
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
000b
00b
0b
0b
0b
1b
0b
0b
1b
0b
Received Target Abort Status (RTAS)
The IGD never gets a Target Abort, therefore this bit is hard
wired to 0.
Signaled Target Abort Status (STAS)
semantics.
DEVSEL Timing (DEVT)
N/A. These bits are hard wired to “00”.
Master Data Parity Error Detected (DPD)
Since Parity Error Response is hard wired to disabled (and
the IGD does not do any parity detection), this bit is hard
wired to 0.
Fast Back-to-Back (FB2B)
the transactions are not to the same agent.
User Defined Format (UDF)
66 MHz PCI Capable (66C)
N/A - hard wired to 0.
Capability List (CLIST)
This bit is set to 1 to indicate that the register at 34h
provides an offset into the function's PCI Configuration
Space containing a pointer to the location of the first item in
the list.
Interrupt Status (INTSTS)
This bit reflects the state of the interrupt in the device. Only
when the Interrupt Disable bit in the command register is a
0 and this Interrupt Status bit is a 1, will the devices INTx#
signal be asserted.
Reserved
hard wired to 0. The IGD does not use target abort
hard wired to 1. The IGD accepts fast back-to-back when
hard wired to 0.
(Sheet 2 of 2)
Description
227