CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 356

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

356
Bit
25
24
Access
RO
RO
Default
Value
0b
0b
Interrupt Remapping Enable (IRE)
This field is valid only for implementations supporting
interrupt remapping.
0 = Disable interrupt-remapping hardware
1 = Enable interrupt-remapping hardware
Hardware reports the status of the interrupt remapping
enable operation through the IRES field in the Global Status
register.
There may be active interrupt requests in the platform when
software updates this field. Hardware must enable or
disable interrupt-remapping logic only at deterministic
transaction boundaries, so that any in-flight interrupts are
either subject to remapping or not at all.
Hardware implementations must drain any in-flight
interrupts requests queued in the Root-Complex before
completing the interrupt-remapping enable command and
reflecting the status of the command through the IRES field
in the Global Status register.
The value returned on a read of this field is undefined.
Set Interrupt Remap Table Pointer (SIRTP)
This field is valid only for implementations supporting
interrupt-remapping.
Software sets this field to set/update the interrupt
remapping table pointer used by hardware. The interrupt
remapping table pointer is specified through the Interrupt
Remapping Table Address register.
Hardware reports the status of the interrupt remapping
table pointer set operation through the IRTPS field in the
Global Status register.
The interrupt remap table pointer set operation must be
performed before enabling or re-enabling (after disabling)
interrupt-remapping hardware through the IRE field.
After an interrupt remap table pointer set operation,
software must globally invalidate the interrupt entry cache.
This is required to ensure hardware uses only the interrupt-
remapping entries referenced by the new interrupt remap
table pointer, and not any stale cached entries.
While interrupt remapping is active, software may update
the interrupt remapping table pointer through this field.
However, to ensure valid in-flight interrupt requests are
deterministically remapped, software must ensure that the
structures referenced by the new interrupt remap table
pointer are programmed to provide the same remapping
results as the structures referenced by the previous
interrupt remap table pointer.
Clearing this bit has no effect. The value returned on a read
of this field is undefined.
(Sheet 4 of 5)
Processor Configuration Registers
Description
Datasheet