CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 87
CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
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Processor Configuration Registers
1.9.8
Datasheet
C0DRA23 - Channel 0 DRAM Rank 2,3 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
See C0DRA01.
15:8
7:0
Bit
Access
RW-L
RW-L
Default
Value
00h
00h
Channel 0 DRAM Rank-3 Attributes (C0DRA3)
This register defines DRAM pagesize/number-of-banks for
Rank 3 for given channel.
See table in register description for programming.
This register is locked by Intel ME stolen Memory lock.
Channel 0 DRAM Rank-2 Attributes (C0DRA2)
This register defines DRAM pagesize/number-of-banks for
Rank 2 for given channel.
See table in register description for programming.
This register is locked by Intel ME stolen Memory lock.
0/0/0/MCHBAR
20A-20Bh
0000h
RW-L
16 bits
Description
87
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