CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 285

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.18.23
Datasheet
IECTL_REG - Invalidation Event Control Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the invalidation event interrupt control bits. This register is treated
as RsvdZ by implementations reporting Queued Invalidation (QI) as not supported in
the Extended Capability register.
29:0
Bit
31
30
Access
RW
RO
RO
00000000h Reserved
Default
Value
0b
0b
Interrupt Mask (IM)
0 = No masking of interrupt. When a invalidation event
1 = This is the value on reset. Software may mask interrupt
Interrupt Pending (IP)
Hardware sets the IP field whenever it detects an interrupt
condition. Interrupt condition is defined as:
The IP field is kept Set by hardware while the interrupt
message is held pending. The interrupt message could be
held pending due to interrupt mask (IM field) being Set, or
due to other transient hardware conditions. The IP field is
cleared by hardware as soon as the interrupt message
pending condition is serviced. This could be due to either:
• An Invalidation Wait Descriptor with Interrupt Flag (IF)
• If the IWC field in the Invalidation Completion Status
• Hardware issuing the interrupt message due to either
• Software servicing the IWC field in the Invalidation
field Set completed, setting the IWC field in the
Invalidation Completion Status register.
register was already Set at the time of setting this field,
it is not treated as a new interrupt condition.
change in the transient hardware condition that caused
interrupt message to be held pending or due to software
clearing the IM field.
Completion Status register.
0/0/0/VC0PREMAP
A0-A3h
00000000h
RO; RW
32 bits
condition is detected, hardware issues an interrupt
message (using the Invalidation Event Data &
Invalidation Event Address register values).
message generation by setting this field. Hardware is
prohibited from sending the interrupt message when this
field is Set.
Description
285