XCV50-6TQ144C Xilinx Inc, XCV50-6TQ144C Datasheet - Page 20
![IC FPGA 2.5V C-TEMP 144-TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XCV50-6TQ144C
Manufacturer Part Number
XCV50-6TQ144C
Description
IC FPGA 2.5V C-TEMP 144-TQFP
Manufacturer
Xilinx Inc
Series
Virtex™r
Datasheet
1.XCV100-5PQ240C.pdf
(76 pages)
Specifications of XCV50-6TQ144C
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
384
Total Ram Bits
32768
Number Of I /o
98
Number Of Gates
57906
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Case
TQFP144
Dc
03+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCV50-6TQ144C
Manufacturer:
XIL
Quantity:
1 238
Company:
Part Number:
XCV50-6TQ144C
Manufacturer:
XILINX
Quantity:
988
Virtex™ 2.5 V Field Programmable Gate Arrays
3. At the rising edge of CCLK: If BUSY is Low, the data is
4. Repeat steps 2 and 3 until all the data has been sent.
Module 2 of 4
16
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this has happened.
DATA[0:7]
WRITE
CCLK
BUSY
CS
5
3
1
Write
Figure 16: Write Operations
www.xilinx.com
1-800-255-7778
Write
2
5. De-assert CS and WRITE.
A flowchart for the write operation appears in
Note that if CCLK is slower than f
asserts BUSY. In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
No Write
7
Write
4
6
ds003_16_071902
DS003-2 (v2.8.1) December 9, 2002
CCNH
Product Specification
, the FPGA never
Figure
17.
R