XE8805AMI028LF Semtech, XE8805AMI028LF Datasheet

IC DAS 16BIT FLASH 8K MTP 64LQFP

XE8805AMI028LF

Manufacturer Part Number
XE8805AMI028LF
Description
IC DAS 16BIT FLASH 8K MTP 64LQFP
Manufacturer
Semtech
Datasheet

Specifications of XE8805AMI028LF

Applications
Sensing Machine
Core Processor
RISC
Program Memory Type
FLASH (22 kB)
Controller Series
XE8000
Ram Size
512 x 8
Interface
UART, USRT
Number Of I /o
24
Voltage - Supply
2.4 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Supply Voltage Range
2.4V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
No. Of Pins
64
For Use With
XE8000MP - PROG BOARD AND PROSTART2 CARD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XE8805AMI028LF
Manufacturer:
Semtech
Quantity:
10 000
Part Number:
XE8805AMI028LF
Manufacturer:
SEMTECH/美国升特
Quantity:
20 000
XE8805/05A – SX8805R
Machine
ZoomingADC™ and buffered DACs
General Description
The XE8805A is a data acquisition ultra low-
power low-voltage system on a chip (SoC) with a
high efficiency microcontroller unit embedded
(MCU), allowing for 1 MIPS at 300uA and 2.4 V,
and multiplying in one clock cycle.
The
acquisition path with the 16+10 bits ZoomingADC
and two buffered DACs.
The XE8805A is available with on chip ROM (the
SX8805) or Multiple-Time-Programmable (MTP)
program memory.
Applications
Rev 1 January 2006
Portable, battery operated instruments
Current loop powered instruments
Wheatstone bridge interfaces
Pressure and chemical sensors
HVAC control
Metering
Sports watches, wrist instruments
XE8805A
includes
a
high
Data Acquisition with 16+10 bit
resolution
Key product Features
Ordering Information
XE8805AMI028LF
XE8805AMI000
XE8805MI028*
SX8805Rxxx
Low-power, high resolution ZoomingADC
Low-voltage low-power controller operation
22 kByte (8 kInstruction) MTP
520 Byte RAM data memory
RC and crystal oscillators
5 reset, 22 interrupt, 8 event sources
8 bit and 16 bit buffered DACs
100 years MTP Flash retention at 55°C
Product
*Not for new designs
**Extended temperature range on request
0.5 to 1000 gain with offset cancellation
up to 16 bits analog to digital converter
up to 13 inputs multiplexer
2 MIPS with 2.4 V to 5.5 V operation
300 µA at 1 MIPS over voltage range
XE8805/05A Sensing Machine
with Zooming ADC and DACs
Temperature range
-40°C to 85 °C**
-40°C to 85 °C
-40°C to 85 °C
-40°C to 85 °C
Data Acquisition MCU
Sensing
Memory type
ROM
MTP
MTP
MTP
www.semtech.com
Package
LQFP64
LQFP64
die

Related parts for XE8805AMI028LF

XE8805AMI028LF Summary of contents

Page 1

... DACs • 100 years MTP Flash retention at 55°C Ordering Information Product Temperature range XE8805MI028* XE8805AMI000 XE8805AMI028LF SX8805Rxxx -40° °C** *Not for new designs **Extended temperature range on request Data Acquisition MCU Sensing Memory type Package -40° °C ...

Page 2

... Chapter 16 Acquisition Chain (ZoomingADC™) Chapter 17 Voltage multiplier Chapter 18 Signal D/A (DAS) Chapter 19 Bias D/A (DAB) Chapter 20 Counters/Timers/PWM Chapter 21 The Voltage Level Detector Chapter 22 XE8805/05A Dimensions © Semtech 2006 XE8805/05A Sensing Machine Data Acquisition MCU with Zooming ADC and DACs www.semtech.com ...

Page 3

... General Overview CONTENTS 1.1 Top schematic 1.1.1 General description 1.1.2 XE8805 vs XE8805A 1.2 Pin map 1.2.1 Bare die 1.2.2 LQFP-64 1.3 Pin assignment © Semtech 2006 1-1 XE8805/05A 1-2 1-2 1-4 1-4 1-4 1-5 1-6 www.semtech.com ...

Page 4

... The Port bit parallel input port. It can also generate interrupts, events or a reset. It can be used to input external clocks for the timer/counter/PWM block. The Port general purpose 8 bit parallel I/O port. The USRT (universal synchronous receiver/transmitter) contains some simple hardware functions in order to simplify the software implementation of a synchronous serial link. © Semtech 2006 1-2 XE8805/05A www.semtech.com ...

Page 5

... Figure 1-1. Block schematic of the XE8805/05A circuit. The UART (universal asynchronous receiver/transmitter) contains a full hardware implementation of the asynchronous serial link. The counters/timers/PWM can take their clocks from internal or external sources (on Port A) and can generate interrupts or events. The PWM is output on Port B. © Semtech 2006 MEMORY B address PORT A ...

Page 6

... PC(3) (52.6, 1328.5) VSS (52.6, 1113.5) PC(4) (52.6, 898.5) PC(5) (52.6, 683.5) PC(6) (52.6, 468.5) PC(7) Figure 1-2. Die dimensions and pin coordinates (in µm) © Semtech 2006 AC_R(0) AC_R(1) VSS AC_A(0) AC_A(1) AC_A(2) AC_A(3) AC_A(4) VBAT AC_A(5) AC_A(6) AC_A(7) ...

Page 7

... PA(3) 5 PA(4) 6 PA(5) 7 PA(6) 8 PA(7) 9 PC(0) 10 PC(1) 11 PC(2) 12 PC(3) 13 PC(4) 14 PC(5) 15 PC(6) 16 PC(7) 17 PB(0) 18 PB(1) 19 PB(2) 20 PB(3) © Semtech 2006 15 10 Figure 1-3. LQFP-64 pin map Package pin name 33 VPP/TEST AC_R(3) 36 AC_R(2) 37 AC_A(7) 38 AC_A(6) 39 AC_A(5) 40 AC_A(4) 41 AC_A(3) 42 AC_A(2) 43 AC_A(1) 44 AC_A(0) 45 AC_R(1) 46 ...

Page 8

... Table 1-3 gives a more detailed pin map for the different pins. It also indicates the possible I/O configuration of these pins. The indications in blue bold are the configuration at start-up. The pins CNTx pins are possible counter inputs, PWMx are possible PWM outputs. © Semtech 2006 Package pin name ...

Page 9

... PB(2) 20 PB(3) 21 USRT_S0 PB(4) 22 USRT_S1 PB(5) 23 PB(6) UART_Tx 24 PB(7) UART_Rx 25 DAB_R_P 26 DAB_R_M 27 DAB_OUT 28 DAB_AO_P 29 DAB_AO_M 30 DAB_AI_P 31 DAB_AI_M 33 VPP TEST 35 AC_R(3) 36 AC_R(2) 37 AC_A(7) 38 AC_A(6) 39 AC_A(5) 40 AC_A(4) 41 AC_A(3) 42 AC_A(2) 43 AC_A(1) 44 AC_A(0) 45 AC_R(1) 46 AC_R(0) 51 DAS_OUT 52 DAS_AI_P 53 DAS_AI_M 54 DAS_AO 55 VBAT © Semtech 2006 I/O configuration ...

Page 10

... OSCOUT 63 OSCIN Pin map table legend: blue bold: configuration at start up AI: analog input AO: analog output DI: digital input DO: digital output OD: nMOS open drain output PU: pull-up resistor POWER: power supply Table 1-3. Pin description table © Semtech 2006 I/O configuration 1-8 XE8805/05A www.semtech.com ...

Page 11

... Absolute maximum ratings 2.2 Operating range 2.3 Supply configurations 2.3.1 Flash circuit 2.3.2 ROM circuit 2.4 Current consumption 2.5 Operating speed 2.5.1 Flash version 2.5.2 ROM circuit version © Semtech 2006 2-1 XE8805/05A 2-2 2-2 2-3 2-3 2-3 2-5 2-6 2-6 2-6 www.semtech.com ...

Page 12

... The capacitor may be omitted when VREG is connected to VBAT. 2. The capacitor on VMULT is optional. The capacitor has to be present if the multiplier is enabled. The multiplier has to be enabled if VBAT<3.0V. All specifications in this document are valid for the complete operating range unless otherwise specified. © Semtech 2006 Min. Max. Note -0.3 6 ...

Page 13

... In this case, the internal voltage regulator is used in order to maintain low power consumption independent from the supply voltage. The capacitor on VREG has to be connected at all times (value in Table 2-3) to guarantee proper operation of the device. The capacitor on VMULT has to be connected only when VBAT<3V. © Semtech 2006 Min. Max. ...

Page 14

... Figure 2-4). In this configuration, the circuit can not be used above 3.3V. VBAT VREG VMULT VSS Figure 2-3. Supply voltage connections for high speed operation of the ROM version. © Semtech 2006 2.4V – 5.5V C vreg C vmult 2.15V – 3.3V ...

Page 15

... PGA and ADC. The power consumption of the ROM version of the circuit is identical configured as shown in Figure 2-2. In the high speed configuration, the current consumption will increase proportional with VBAT. © Semtech 2006 3.3 VBAT (V) ...

Page 16

... Figure 2-6. Guaranteed speed as a function of supply voltage and for different maximal temperatures using the voltage regulator. 2.5.2.2 High speed supply configuration In the high speed supply configuration of Figure 2-3, the guaranteed speed of the circuit is shown in Figure 2-7. © Semtech 2006 85°C 45° ...

Page 17

... VBAT (V) Figure 2-7. Guaranteed speed as a function of supply voltage and for three temperature ranges when VREG=VBAT. © Semtech 2006 125°C 2.8 3 3.2 3.4 2-7 XE8805/05A www.semtech.com ...

Page 18

... CPU CONTENTS 3.1 CPU description 3.2 CPU internal registers 3.3 CPU instruction short reference © Semtech 2006 3-1 XE8805/05A 3-2 3-2 3-4 www.semtech.com ...

Page 19

... The program counter (PC bit register that indicates the address of the instruction that has to be executed. The stack ( used to memorise the return address when executing subroutines or interrupt routines. n Instruction memory 22bit Figure 3-1. CPU internal registers © Semtech 2006 core makes it possible to compute program counter stack CPU ...

Page 20

... For an arithmetic operation with unsigned numbers occurrence of an overflow during an addition (or equivalent occurrence of an underflow during a subtraction (or equivalent). V overflow This flag is used in shift or arithmetic operations. For arithmetic or shift operations with signed numbers overflow or underflow occurs. Table 3-3. Flag description © Semtech 2006 3-3 XE8805/05A www.semtech.com ...

Page 21

... Cpl2c reg Cpl2c reg, eaddr Inc reg1, reg2 Inc reg Inc reg, eaddr Incc reg1, reg2 Incc reg Incc reg, eaddr Dec reg1, reg2 © Semtech 2006 eaddr Operation PC := addr[15: true then PC := addr[15: true then (n>1 PC+ addr[15:0] n (n>1 PC+ n PC+ addr[15: PC+ ...

Page 22

... Setb reg,#bit[2: Clrb reg,#bit[2: Invb reg,#bit[2: © Semtech 2006 a := reg-1; if a=hFF then else reg a := DM(eaddr)-1; if a=hFF then else reg2-(1-C); if a=hFF and C=0 then else reg-(1-C); if a=hFF and C=0 then else DM(eaddr)-(1-C); if a=hFF and C=0 then else ...

Page 23

... GT op1>op2 GE op1≥op2 LT op1<op2 LE op1≤op2 Table 3-6. Jump condition description © Semtech 2006 a[ a[ xor V; a[ full; a[ empty a := reg << a[ reg[ DM(eaddr)<<1; a[0] := DM(eaddr)[7] reduces the CPU frequency (divn=nodiv, div2, div4, div8, div16) halts the CPU no operation DM(eaddr) and will simultaneously execute the index operation ...

Page 24

... Acquisition chain registers (h0060-h0067) 4.2.13 Signal D/A registers (h0074-h0077) 4.2.14 Bias D/A registers (h0078-h0079) 4.2.15 Voltage multiplier (h007C) 4.2.16 Voltage Level Detector registers (h007E-h007F) 4.2.17 RAM (h0080-h027F) © Semtech 2006 4-1 XE8805/05A 4-2 4-2 4-3 4-4 4-4 4-4 4-5 4-5 4-5 ...

Page 25

... The access mode of the different bits (see Table 4-1 for code description) 4. The reset source and reset value of the different bits The reset source coding is given in Table 4-2. To get a full description of the reset sources, please refer to the reset block chapter. © Semtech 2006 CPU ...

Page 26

... Reg00 h0000 Reg01 h0001 Reg02 h0002 Reg03 h0003 Reg04 h0004 Reg05 h0005 Reg06 h0006 Reg07 h0007 Table 4-3. Low power data registers © Semtech 2006 Reg00[7:0] rw, xxxxxxxx,- Reg01[7:0] rw,xxxxxxxx,- Reg02[7:0] rw,xxxxxxxx,- Reg03[7:0] rw,xxxxxxxx,- Reg04[7:0] rw,xxxxxxxx,- Reg05[7:0] rw,xxxxxxxx,- Reg06[7:0] rw,xxxxxxxx,- Reg07[/:0] ...

Page 27

... Port B (h0028-h002F) Name Address 7 6 RegPBOut h0028 RegPBIn h0029 RegPBDir h002A RegPBOpen h002B RegPBPullup h002C RegPBAna h002D r0 r0 Table 4-6. Port B registers © Semtech 2006 EnBusError EnResWD rw,0,cold rw,0,cold r0 r0 ResetBusError ResetfromportA ResetWD ResPad rc, 0, cold rc, 0, cold rc, 0, cold rc,0,cold EnExtClock ...

Page 28

... CntIrqA Counter/Timer A (counter block) CntIrqB Counter/Timer B (counter block) CntIrqC Counter/Timer C (counter block) CntIrqD Counter/Timer D (counter block) 128Hz Low prescaler (clock block) 1Hz Low prescaler (clock block) PAEvn[1:0] Port A Table 4-9. Event source description © Semtech 2006 PCOut[7:0] rw,00000000,pconf PCIn[7:0] r,-,- PD1Dir[7:0] rw,00000000,pconf ...

Page 29

... PAIrq[7:0] Port A UartIrqRx UART reception UartIrqTx UART transmission UrstCond1 USRT condition 1 UsrtCond2 USRT condition 2 VldIrq Voltage level detector IrqAC Acquisition chain end of conversion interrupt Table 4-11. Interrupt source description © Semtech 2006 CntIrqA CntIrqC r0 rc1,0,sys rc1,0,sys r0 PAIrq[5] PAIrq[4] 1Hz VldIrq rc1,0,sys ...

Page 30

... Name Address 7 6 RegCntA h0058 RegCntB h0059 RegCntC h005A RegCntD h005B RegCntCtrlCk CntDCkSel[1:0] h005C rw,xx,- CntDDownUp CntCDownUp RegCntConfig1 h005D rw,x,- rw,x,- RegCntConfig2 CapSel[1:0] h005E rw,00,sys RegCntOn h005F r0 r0 Table 4-14. Counter/timer/PWM register description. © Semtech 2006 UsrtEnWaitCond1 UsrtWaitS0 rw,0,sys r0 r0 r,0,sys ...

Page 31

... RegDabIn h0078 RegDabCfg h0079 r0 r0 Table 4-17. Bias D/A register description 4.2.15 Voltage multiplier (h007C) Name Address 7 6 RegVmultCfg0 h007C r0 r0 Table 4-18. VMULT register. © Semtech 2006 OUT[7:0] r,0,sys OUT[15:8] r,0,sys SET_OSR[2:0] rw,010,sys IB_AMP_PGA[1:0] ENABLE[3:0] rw,11,sys rw,0000,sys PGA2_GAIN[1:0] PGA2_OFFSET[3:0] rw,00,sys ...

Page 32

... Table 4-19. Voltage level detector register description 4.2.17 RAM (h0080-h027F) The 512 RAM bytes can be accessed for read and write operations. The RAM has no reset function. Variables stored in the RAM should be initialised before use since they can have any value at circuit start up. © Semtech 2006 ...

Page 33

... System Block 5.1 Overview 5.2 Operating mode © Semtech 2006 5-1 XE8805/05A 5-2 5-2 www.semtech.com ...

Page 34

... The start-up time of the oscillator will then be longer however. Note recommended to insert a NOP instruction after the instruction that sets the circuit in sleep mode because this instruction can be executed when the sleep mode is left using the resetfromportA. © Semtech 2006 5-2 XE8805/05A ...

Page 35

... Halt instruction ACTIVE Interrupt/event normal mode Figure 5-1. XE8805 operating modes. © Semtech 2006 por por padreset portA reset STAND-BY set bit sleep low current very low current 5-3 XE8805/05A SLEEP ...

Page 36

... Programmable Port A input combination 6.5.4 Watchdog reset 6.5.5 BusError reset 6.5.6 Sleep mode 6.6 Control register description and operation 6.7 Watchdog 6.8 Start-up and watchdog specifications © Semtech 2006 6-1 XE8805/05A 6-2 6-2 6-2 6-3 6-4 6-4 6-4 6-4 6-4 6-4 ...

Page 37

... ResPadSleep resetcold Table 6-2. RegSysReset register © Semtech 2006 Function enables Sleep mode 0: sleep mode is disabled 1: sleep mode is enabled enables the resetpconf signal when the resetglobal is active 0: resetpconf is disabled 1: resetpconf is enabled enables reset from BusError 0: BusError reset source is disabled 1: BusError reset source is enabled ...

Page 38

... Asserted Sleep - (1) For the circuits XE8801A and XE8805A (2) For the circuits XE8801 and XE8805 Table 6-4. Internal reset assertion as a function of the reset source. © Semtech 2006 Function unused Watchdog Key bit 3 Watchdog counter bit 3 Watchdog Key bit 2 Watchdog counter bit 2 ...

Page 39

... Note: When a reset pin wakes up the chip from the sleep mode, ResPad and ResPadSleep bits are equal at 1. The last bit concerns the sleep mode control (see system documentation for the sleep mode description). © Semtech 2006 bit in the RegSysCtrl register has been set and if the EnResetWD ...

Page 40

... At start-up of the circuit, the POR (power-on-reset) block generates a reset signal during t software execution after this period (see system chapter). The POR is intended to force the circuit in a correct state at start-up. For precise monitoring of the supply voltage, the voltage level detector (VLD) has to be used. © Semtech 2006 6-5 XE8805/05A ...

Page 41

... Note: 3) For the circuit versions XE8801 and XE8805. Gives the time the reset is active after the falling edge of the RESET pin. Note: 4) For the circuit versions XE8801A and XE8805A. Gives the time the reset is active after the falling edge of the RESET pin. © Semtech 2006 Unit Min Typ ...

Page 42

... Clock sources 7.5.1 RC oscillator 7.5.2 Xtal oscillator 7.5.3 External clock 7.6 Clock source selection 7.7 RegSysMisc Description 7.8 Prescalers 7.9 32 kHz frequency selector © Semtech 2006 7-1 XE8805/05A 7-2 7-2 7-2 7-3 7-4 7-4 7-6 7-7 7-8 7-8 7-9 7-9 www.semtech.com ...

Page 43

... RCOnPA0 2 DebFast 1 OutputCkXtal 0 OutputCpuCk pos. RegSysPre0 7 ResPre © Semtech 2006 rw Reset rw 0 resetsleep Select speed for cpuck, 0=RC, 1=xtal or external clock r 0 resetcold External clock detected, 1=available rw 0 resetcold Enable for external clock, 1=enabled rw 1 resetcold Enable Rcbias (reduces start-up time of RC). ...

Page 44

... CkXtal 1 OSCIN Xtal CpuSel EnXtal and not(ExtClk or EnExtClk) 7.4 Interrupts and events map Interrupt Interrupt source IrqPre1 Ck128Hz IrqPre2 Ck1Hz © Semtech 2006 rw reset r 00 Unused rw 0 resetcold Reserved rw 0 resetcold Low/high freq. range (low= resetcold RC coarse trim bit 3 rw ...

Page 45

... The frequency of the oscillator is therefor given by: ⋅(1+9⋅RcFreqRange)⋅(1+RcFreqCoarse)⋅(1.014 Rcmin with f the RC oscillator frequency if the registers are all 0. At higher frequencies, the frequency may deviate Rcmin from the value predicted by the equation. © Semtech 2006 RcFreqFine 7-4 XE8805/05A www.semtech.com ...

Page 46

... Note 3: frequency shift as a function of VBAT while the regulator is short-circuited to VBAT. The tolerances on the minimal frequency and the drift with supply or temperature can be cancelled using the software DFLL (digital frequency locked loop) which uses the crystal oscillator as a reference frequency. © Semtech 2006 0001 0011 ...

Page 47

... Capacitance OSCIN-VSS Cp_oscin Capacitance OSCOUT-VSS Cp_oscout Capacitance OSCIN-OSCOUT Cp_ oscin_oscout The oscillator characteristics are given in Table 7-10. The characteristics are valid only if the crystal and board layout meet the specifications above. © Semtech 2006 Min Typ Max 32768 8 100 1.8 2 ...

Page 48

... The external clock has to satisfy the specifications in the table below. Correct behavior of the circuit can not be guaranteed if the external clock signal does not respect the specifications below. Symbol Description F External clock EXT frequency PW_1 Pulse 1 width PW_0 Pulse 0 width Table 7-11. External clock specifications. © Semtech 2006 Min Typ Max Unit 32768 -100 300 ppm Min ...

Page 49

... Bit OutputCkXtal allows to show the Xtal clock on PB[3]. The EnableXtal bit must be set to 1 else PB[3] equals 0 (see port B documentation to set up the port B). Bit OutputCpuCk allows to show the CpuClock on PB[2] (see port B documentation). © Semtech 2006 Clock targets Note 1 Cpuck ...

Page 50

... A decoder is used to select from the high prescaler the frequency tap that is the closest to 32 kHz to operate the low prescaler when the Xtal is not running. In this case, the RC oscillator frequency of ±50% will also be valid for the low prescaler frequency outputs. © Semtech 2006 7-9 XE8805/05A ...

Page 51

... IRQ - Interrupt handler 8.1 Features 8.2 Overview 8.3 Register map © Semtech 2006 8-1 XE8805/05A 8-2 8-2 8-2 www.semtech.com ...

Page 52

... RegIrqHig 7 RegIrqHig[7] 6 RegIrqHig[6] 5 RegIrqHig[5] 4 RegIrqHig[4] 3 RegIrqHig[3] 2 RegIrqHig[2] 1 RegIrqHig[1] 0 RegIrqHig[0] © Semtech 2006 rw reset r 0 resetsystem interrupt #23 (high priority) c1 clear interrupt #23 when 1 is written r 0 resetsystem interrupt #22 (high priority) c1 clear interrupt #22 when 1 is written r 0 resetsystem interrupt #21 (high priority) c1 clear interrupt #21 when 1 is written ...

Page 53

... RegIrqEnHig 7 RegIrqEnHig[7] 6 RegIrqEnHig[6] 5 RegIrqEnHig[5] 4 RegIrqEnHig[4] 3 RegIrqEnHig[3] 2 RegIrqEnHig[2] 1 RegIrqEnHig[1] 0 RegIrqEnHig[0] © Semtech 2006 rw reset r 0 resetsystem interrupt #15 (mid priority) c1 clear interrupt #15 when 1 is written r 0 resetsystem interrupt #14 (mid priority) c1 clear interrupt #14 when 1 is written r 0 resetsystem interrupt #13 (mid priority) c1 clear interrupt #13 when 1 is written ...

Page 54

... RegIrqEnLow[4] 3 RegIrqEnLow[3] 2 RegIrqEnLow[2] 1 RegIrqEnLow[1] 0 RegIrqEnLow[0] pos. RegIrqPriority 7-0 RegIrqPriority pos. RegIrqIrq 7 IrqHig 1 IrqMid 0 IrqLow © Semtech 2006 rw reset rw 0 resetsystem 1= enable interrupt # resetsystem 1= enable interrupt # resetsystem 1= enable interrupt # resetsystem 1= enable interrupt # resetsystem 1= enable interrupt # resetsystem 1= enable interrupt # resetsystem 1= enable interrupt #9 rw ...

Page 55

... Event Handler 9.1 Features 9.2 Overview 9.3 Register map © Semtech 2006 9-1 XE8805/05A 9-2 9-2 9-2 www.semtech.com ...

Page 56

... Register map pos. RegEvn 7 RegEvn[7] 6 RegEvn[6] 5 RegEvn[5] 4 RegEvn[4] 3 RegEvn[3] 2 RegEvn[2] 1 RegEvn[1] 0 RegEvn[0] © Semtech 2006 rw reset r 0 resetsystem event #7 (high priority) c1 clear event #7 when written resetsystem event #6 (high priority) c1 clear event #6 when written resetsystem event #5 (high priority) c1 clear event #5 when written 1 r ...

Page 57

... RegEvnEn[5] 4 RegEvnEn[4] 3 RegEvnEn[3] 2 RegEvnEn[2] 1 RegEvnEn[1] 0 RegEvnEn[0] pos. RegEvnPriority 7-0 RegEvnPriority pos. RegEvnEvn 7 EvnHig 0 EvnLow © Semtech 2006 rw reset rw 0 resetsystem 1= enable event # resetsystem 1= enable event # resetsystem 1= enable event # resetsystem 1= enable event # resetsystem 1= enable event # resetsystem 1= enable event # resetsystem 1= enable event #1 rw ...

Page 58

... Low Power RAM 10.1 Features 10.2 Overview 10.3 Register map © Semtech 2006 10-1 XE8805/05A 10-2 10-2 10-2 www.semtech.com ...

Page 59

... Reg03 pos. Reg04 7-0 Reg04 pos. Reg05 7-0 Reg05 pos. Reg06 7-0 Reg06 pos. Reg07 7-0 Reg07 © Semtech 2006 rw reset function rw XXXXXXXX low-power data memory Table 10-1: Reg00 rw reset function rw XXXXXXXX low-power data memory Table 10-2: Reg01 rw reset function ...

Page 60

... Port A 11.1 Features 11.2 Overview 11.3 Register map 11.4 Interrupts and events map 11.5 Port A (PA) Operation 11.6 Port A electrical specification © Semtech 2006 11-1 XE8805/05A 11-2 11-2 11-3 11-3 11-4 11-5 www.semtech.com ...

Page 61

... PA[0] to PA[3] can be used as clock inputs for the counters/timers/PWM (product dependent) • PA[0] can be used to enable the RC oscillator 11.2 Overview Port general purpose 8 bit wide digital input port, with interrupt capability. Figure 11-1 shows its structure. VBat © Semtech 2006 Port A RegPAPullup 8 RegPADebounce RegPACtrl debounce 0 8 RegPAIn 8 ...

Page 62

... RegIrqMid[5] pa_irqbus[4] RegIrqMid[4] pa_irqbus[1] RegIrqMid[1] pa_irqbus[0] RegIrqMid[0] pa_irqbus[7] RegIrqLow[7] pa_irqbus[6] RegIrqLow[6] pa_irqbus[3] RegIrqLow[3] pa_irqbus[2] RegIrqLow[2] © Semtech 2006 rw reset description r pad PA[7] to PA[0] input value Table 11-1: RegPAIn rw reset description 00000000 r w resetpconf Table 11-2: RegPADebounce rw reset description ...

Page 63

... PAReset[7] AND PAReset[6] AND PAReset[5] AND ... AND PAReset[0] PAReset[x] is itself a logical function of the corresponding pin PA[x]. One of four logical functions can be selected for each pin by writing into two registers RegPARes0 and RegPARes1 as shown in Table 11-8. © Semtech 2006 Clock filter 0 ...

Page 64

... Port A electrical specification Sym description V Input high voltage INH V Input low voltage INL R Pull-up resistance PU Cin Input capacitance Note 1: this value is indicative only since it depends on the package. Table 11-9. Port A electrical specification. © Semtech 2006 PARes0[x] PAReset[ not(PA[x min typ max unit Comments ...

Page 65

... Port B analog configuration 12.5.2 Port B analog function specification 12.6 Port B function capability 12.7 Port B digital capabilities 12.7.1 Port B digital configuration 12.7.2 Port B digital function specification © Semtech 2006 12-1 XE8805/05A 12-2 12-2 12-2 12-3 12-3 12-3 12-4 12-4 12-5 12-5 12-6 www ...

Page 66

... PBAna [ resetpconf 1 PBAna [ resetpconf 0 PBAna [ resetpconf © Semtech 2006 reset description in digital mode Pad PB[7-0] output value Table 12-1: RegPBOut reset description in digital mode Pad PB[7-0] input status Table 12-2: RegPBIn reset description in digital mode Pad PB[7-0] direction (0=input) Table 12-3: RegPBDir ...

Page 67

... For even values of x, the selection bits are in the register RegPBDir (see Table 12-9 odd, PBOut[x, x- Table 12-8: Selection of the analog lines for PB[x] when x is odd and PBAna[ © Semtech 2006 usage (priority) functions (medium) uart Rx uart Tx usrt S1 usrt S0 32 kHz ...

Page 68

... This overrides the value contained in PBOut(3). However, PBDir(3) must be set to 1. The duty cycle of the clock signal is about 50%. Similarly, if OutputCkCpu is set in RegSysMisc, the CPU frequency is output on PB[2]. This overrides the value contained in PBOut(2). However, PBDir(2) must be set to 1. © Semtech 2006 PBPullup[x] PB[x] selection on 1 ...

Page 69

... After power-on reset, the Port B is configured as an input port without pull-up. The input buffer is always active, except in analog mode. This means that the Port B input should be a valid digital value at all times unless the pin is set in analog mode. Violating this rule may lead to higher power consumption. © Semtech 2006 12-5 XE8805/05A ...

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... Input low voltage INL V Output high voltage OH V Output low voltage OL R Pull-up resistance PU Cin Input capacitance Note 1: this value is indicative only since it depends on the package. © Semtech 2006 min typ max unit Comments 0.7*VBAT VBAT V VSS 0.2*VBAT V VBAT-0.4 VBAT V VSS VSS+0 ...

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... Port C 13.1 Features 13.2 Overview 13.3 Port C (PC) Operation 13.4 Register map 13.5 Port C electrical specification © Semtech 2006 13-1 XE8805/05A 13-2 13-2 13-2 13-2 13-3 www.semtech.com ...

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... There are three registers in the Port C (PC), namely RegPCIn, RegPCOut and RegPCDir. Table 13-1 to Table 13-3 show the mapping of control bits and functionality of these registers. Pos. RegPCIn Rw Reset 7-0 PCIn r Table 13-1. RegPCIn © Semtech 2006 Port C 8 RegPCOut 8 RegPCDir 8 RegPCIn Figure 13-1: structure of Port C Description ...

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... Output high voltage OH V Output low voltage OL Cin Input capacitance Note 1: this value is indicative only since it depends on the package. Table 13-4. Port C electrical specification © Semtech 2006 Description pad PC output value Description pad PC direction (0=input) min typ max unit Comments 0.7*VBAT ...

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... Uart on the RC oscillator 14.5.2 Uart on the crystal oscillator 14.6 Function description 14.6.1 Configuration bits 14.6.2 Transmission 14.6.3 Reception 14.7 Interrupt or polling 14.8 Software hints © Semtech 2006 14-1 XE8805/05A 14-2 14-2 14-2 14-3 14-3 14-3 14-4 14-4 14-4 14-5 14-5 14-6 14-7 www ...

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... UartXTx rw 2-0 UartBR(2:0) rw pos. RegUartTx rw 7-0 UartTx rw © Semtech 2006 Reset 0 resetsystem Select input clock RC xtal 0 resetsystem Enable Uart Reception 000 resetsystem RC prescaler selection 0 resetsystem Select parity mode odd even 0 resetsystem Enable parity with parity parity 1 resetsystem Select word length bits bits ...

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... In order to obtain a correct baud rate, the RC oscillator frequency has to be set to one of the frequencies given in the table on the next page. The precision of the obtained baud rate is directly proportional to the frequency deviation with respect to the values in the table. © Semtech 2006 reset description ...

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... The bits UartEnTx is used to enable or disable the transmission. The bits UartEnRx1 and UartEnRx2 are used to enable or disable the reception. When one is set to 1, the reception is enabled. © Semtech 2006 2’457’600 1’843’200 1’228’800 614’400 1’ ...

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... Figure 14-1. Uart transmission timing diagram. 14.6.3 Reception On detection of the start bit, the UartRxBusy bit is set. On detection of the stop bit, the received data are transferred from the internal shift register to the register RegUartRx. At the same time, the UartRxFull bit is set © Semtech 2006 word 1 start b0 b1 ...

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... Reception driven by polling: the UartRxFull bit read and checked. When the RegUartRx register contains new data and has to be read before a new word is received. Transmission driven by polling: the UartTxFull bit is to read and checked. When the RegUartTx register is empty and a new word can be written to it. © Semtech 2006 b0 b6/7 parity ...

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... The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit word length, odd parity, 9600 baud, enable Uart reception). 2. When there is an interrupt, jump Read RegUartRxSta and check if there is no error. 4. Read data in RegUartRx data is not equal to End-Of-Line, then jump End of reception. © Semtech 2006 14-7 XE8805/05A www.semtech.com ...

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... USRT 15.1 Features 15.2 Overview 15.3 Register map 15.4 Interrupts map 15.5 Conditional edge detection 1 15.6 Conditional edge detection 2 15.7 Interrupts or polling 15.8 Function description © Semtech 2006 15-1 XE8805/05A 15-2 15-2 15-2 15-4 15-4 15-4 15-5 15-5 www.semtech.com ...

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... The values that are read in the registers RegUsrtS1 and RegUsrtS0 are not necessarily the same as the values that were written in the register. The read value is read back on the circuit pins, not in the registers. Since the outputs are open drain, a value different from the register value may be forced by an external circuit on the circuit pins. © Semtech 2006 rw reset r ...

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... RegUsrtCond2 7 UsrtCond2 r/c pos. RegUsrtBufferS1 7 UsrtBufferS1 w © Semtech 2006 rw reset “0000” Unused 0 resetsystem Clock stretching flag (0=no stretching), cleared by writing RegUsrtBufferS1 0 resetsystem Enable stretching on UsrtCond1 detection (0=disable resetsystem Enable stretching operation (0=disable) 0 resetsystem Enable USRT operation (0=disable) Table 15-3: RegUsrtCtrl ...

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... USRT interface is enabled (UsrtEnable=1). Condition 1 is asserted for both modes (receiver and transmitter). The UsrtCond1 bit is read only and is cleared by all reset conditions and by writing any data to its address. Condition 1 occurrence also generates an interrupt on Irq_cond1. 15.6 Conditional edge detection © Semtech 2006 rw reset 0000000 Unused 0 resetsystem State ...

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... S0 line is forced low. One can release S0 by writing to the RegUsrtBufferS1 register. The same can be done in combination with condition 1 detection by setting the UsrtEnWaitCond1 bit. Figure 15-4 shows the conditional clock stretching function which is enabled by setting UsrtEnWaitCond1. © Semtech 2006 15-5 XE8805/05A www.semtech.com ...

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... RegUsrtEdgeS0 is set to one on the same S0 rising edge and is cleared by a read operation of the RegUsrtBufferS1 register. The bit therefore indicates that a new value is present in the RegUsrtBufferS1 which has not yet been read UsrtBufferS1 read Reg UsrtBufferS1 UsrtEdgeS0 © Semtech 2006 Figure 15-5: S1 sampling 15-6 XE8805/05A www.semtech.com ...

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... Power Supply Rejection Ratio................................................................................................ 16-30 16.9 Application Hints.................................................................................................................. 16-31 16.9.1 Input Impedance .................................................................................................................... 16-31 16.9.2 PGA Settling or Input Channel Modifications.......................................................................... 16-31 16.9.3 PGA Gain & Offset, Linearity and Noise................................................................................. 16-31 16.9.4 Frequency Response ............................................................................................................. 16-32 16.9.5 Power Reduction.................................................................................................................... 16-33 © Semtech 2006 16-1 XE8805/05A www.semtech.com ...

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... RegAcCfg1, RegAcCfg2, RegAcCfg3, RegAcCfg4 and RegAcCfg5. Table 16-2 to Table 16-9 show the mapping of control bits and functionality of these registers while Table 16-1 gives an overview of these eight. The register map only gives a short description of the different configuration bits. More detailed information is found in subsequent sections. © Semtech 2006 f S PGA1 ...

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... CONT 0 reserved pos. RegAcCfg1 7:6 IB_AMP_ADC[1:0] 5:4 IB_AMP_PGA[1:0] 3:0 ENABLE[3:0] pos. RegAcCfg2 7:6 FIN[1:0] 5:4 PGA2_GAIN[1:0] 3:0 PGA2_OFFSET[3:0] © Semtech 2006 register name RegAcOutLsb RegAcOutMsb RegAcCfg0 RegAcCfg1 RegAcCfg2 RegAcCfg3 RegAcCfg4 RegAcCfg5 Table 16-1: AC registers rw reset description 00000000 r resetsystem Table 16-2: RegAcOutLsb rw ...

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... Note: Over-sampled converters are operated with a sampling frequency f 1'000 times the input signal bandwidth). The sampling frequency to throughput ratio is large (typically 10-500). These converters include digital decimation filtering. They are mainly used for high resolution, and/or low-to-medium speed applications. © Semtech 2006 rw reset ...

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... Inputs AC_A AC_R 2 3 RegACCfg5 RegACCfg4 RegACCfg3 RegACCfg2 RegACCfg1 RegACCfg0 Figure 16-2. ZoomingADC™ detailed functional block diagram © Semtech 2006 (Eq. 1) IN,ADC ⋅ (V) (Eq REF is the total PGA offset. TOT f S PGA1 PGA2 PGA3 V IN GD1 GD2 GD3 OFF2 OFF3 ...

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... PGA2_OFFSET[5:0]. • PGA3_OFFSET: (rw) sets the offset of the third stage between –5.25 and +5.25, with increments of 1/12. The MSB gives the sign (0 → positive, 1 → negative); amplitude is coded with the bits PGA3_OFFSET[5:0]. © Semtech 2006 Bit Position 5 4 ...

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... AMUX(4:0): (rw) AMUX[4] sets the mode (0 AMUX(3) sets the sign (0 straight, 1 • VMUX: (rw) sets the differential reference channel ( read write read & write) © Semtech 2006 4 differential inputs inputs with A(0) = common reference) cross) AMUX[2:0] sets the channel. R(1) and R(0), 1 R(3) and R(2)). ...

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... Note that the flag is set at the effective start of the conversion. Since the ADC is generally synchronized CONV on a lower frequency clock than the CPU, there might be a small delay (max. 1 cycle of the ADC sampling frequency) between the writing of the START or CONT bits and the appearance of BUSY flag. © Semtech 2006 T CONV Internal Trig ...

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... AC_A(6) 10111 AC_A(7) Similarly, the reference voltage is chosen among two differential channels (V AC_R(3)-AC_R(2)) as shown in Table 16-12. The selection bit is VMUX. The reference inputs V (common-mode) can the power supply range. © Semtech 2006 and reference voltage V IN (Eq. 3) (Eq. 4) AMUX[4:0] V ...

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... PGA3: fine gain and offset tuning All gain and offset settings are realized with ratios of capacitors. The user has control over each PGA activation and gain, as well as the offset of stages 2 and 3. These functions are examined hereafter. © Semtech 2006 VMUX V V ...

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... Semtech 2006 PGA2 Offset PGA2_OFFSET[3:0] GDoff (V/V) 2 0000 0 0001 +0.2 0010 +0.4 0011 +0.6 0100 +0.8 0101 +1 1001 -0.2 1010 -0.4 1011 -0.6 1100 -0.8 1101 -1 Table 16-16. PGA2 offset settings PGA3 Gain PGA3_GAIN[6:0] GD (V/V) 3 0000000 0 0000001 1/12(=0.083) ... ...

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... PGA3_GAIN[6:0] and PGA3_OFFSET[6: remain within the signal compliance of the PGA stages, the condition: < ( must be verified. As shown in equation 7, the offset correction is directly proportional to the reference voltage. All drifts and perturbations on the reference voltage will affect the precision of the offset compensation. © Semtech 2006 (Eq. 5) (V) (Eq. 6) (V) (Eq. 7) REF (Eq. 8) 16-12 XE8805/05A at D1 www.semtech.com ...

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... Thus, converter internal offset is eliminated if at least two elementary sequences are ≥ 2). A few additional clock cycles are also required to initiate and end the conversion performed (i. ELCONV properly. Elementary Init Conversion Conversion index 1 Offset + Figure 16-5. Analog-to-digital conversion sequence © Semtech 2006 ⋅ (V) (Eq REF (V/V) (Eq. 10) (V/V) (Eq. 11 ELCONV ...

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... As mentioned previously, the whole conversion sequence is made of a set of N conversions. This number is set with the word SET_NELC[1:0] in power of 2 steps (see Table 16-21) given by: SET_NELC ELCONV © Semtech 2006 (Table 16-19). Three sub-multiples of the internal S Sampling Frequency f FIN[1:0] 01/05 00 1/4⋅ 1/8⋅ ...

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... ADC output, practical resolution is limited to 16 bits, i.e. n ≤ 16. Even if the resolution is truncated to 16 bit by the output register size, it may make sense to set OSR and N higher values in order to reduce the influence of the thermal noise in the PGA (see section 16.8.4). © Semtech 2006 # of Elementary Conversions ...

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... Table 16-25. The output code, expressed in LSBs, corresponds to OSR = ⋅ ⋅ ADC 16 OUT 2 ADC V OSR REF Recalling equation Eq. 9, this can be rewritten as: © Semtech 2006 (s) (Eq. 16 For example, consider an over-sampling ratio of 256, 2 elementary CONV SET_NELC[1: ...

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... Table 16-25. Last forced LSBs in conversion output registers for resolution settings smaller than 16 bits (n < 16) (RegAcOutMsb[7:0] & RegAcOutLsb[7:0]) © Semtech 2006 ⎞ + OSR 1 V ⎟ ⎟ ⋅ ⋅ (LSB) (Eq. 18) REF GDoff TOT V ⎠ ...

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... Table 16-26. ADC & PGA power saving modes and maximum sampling frequency 16.8 Specifications and Measured Curves This section presents measurement results for the acquisition chain. A summary table with circuit specifications and measured curves are given. © Semtech 2006 (V) (Eq. 19) OSR (V) (Eq ...

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... A • +5V, GND = 0V • RC frequency f = 2MHz, sampling frequency f RC • Offsets GDOff = GDOff 2 • Power operation: normal (IB_AMP_ADC[1:0] = IB_AMP_PGA[1:0] = '11') • Resolution: for bits: OSR = 32 and N for bits: OSR = 512 and N © Semtech 2006 = +5V REF IN = 500kHz ELCONV = 2 ELCONV 16-19 XE8805/05A www.semtech.com ...

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... Conversion Time, T CONV Throughput Rate (Continuous Mode), 1/T CONV Nbr of Initialization Cycles, N INIT Nbr of End Conversion Cycles, N END PGA Stabilization Delay DIGITAL OUTPUT ADC Output Data Coding © Semtech 2006 = +25° +5V, GND = 0V +5V REF = 1, offsets GDOff = GDOff = 0. Power operation: normal (IB_AMP_ADC[1:0] = TOT ...

Page 107

... Bias currents in PGAs and ADC set to 1/4 of nominal values, i.e. IB_AMP_PGA[1:0] = ‘00’, IB_AMP_ADC[1:0] = ‘00’. 16.8.3 Linearity 16.8.3.1 Integral non-linearity The integral non-linearity depends on the selected gain configuration. First of all, the non-linearity of the ADC (all PGA stages bypassed) is shown in Figure 16-8. © Semtech 2006 VALUE UNITS MIN TYP MAX +2 ...

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... Increasing the gain further up to 1000 will further increase the linearity since the signal becomes very small in the first two stages. The signal is full scale at the output of stage 3 and as shown in Figure 16-9 to Figure 16-12, this stage has very good linearity. © Semtech 2006 16-22 XE8805/05A ...

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... Figure 16-9. Integral non-linearity of the ADC and with gain of 1 (PGA1 and PGA2 disabled, PGA3=1, Figure 16-10. Integral non-linearity of the ADC and gain of 2 (PGA1 and PGA2 disabled, PGA3=2 Figure 16-11. Integral non-linearity of the ADC and gain of 5 (PGA1 and PGA2 disabled, PGA3=5, © Semtech 2006 reference voltage of 5V) reference voltage of 5V) ...

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... Figure 16-12. Integral non-linearity of the ADC and gain of 10 (PGA1 and PGA2 disabled, PGA3=10, Figure 16-13. Integral non-linearity of the ADC and gain of 20 (PGA1 and PGA2=10, PGA3=2, © Semtech 2006 reference voltage of 5V) reference voltage of 5V) 16-24 XE8805/05A www.semtech.com ...

Page 111

... Figure 16-15. Integral non-linearity of the ADC and gain of 100 (PGA1=10 and PGA3=10, PGA2 16.8.3.2 Differential non-linearity The differential non-linearity is generated by the ADC. The PGA does not add differential non-linearity. Figure 16-16 shows the differential non-linearity. © Semtech 2006 reference voltage of 5V) disabled, reference voltage of 5V) 16-25 XE8805/05A ...

Page 112

... Standard deviation at ADC output (LSB) Output rms noise (µV) Note: see noise model of Figure 16-18 and equation Eq. 21. Table 16-27. PGA noise measurements ( bits, OSR = 512, N © Semtech 2006 should result in a constant output code. However, because of circuit noise, the ⋅ + ⋅ ...

Page 113

... Finally, these gain errors can be calibrated by the software at the same time with the gain errors of the sensor for instance. Figure 16-19 shows gain error drift vs. temperature for different PGA gains. The curves are expressed Full- Scale Range (FSR) normalized to 25°C. © Semtech 2006 ...

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... Quiescent current consumption vs. temperature is depicted in Figure 16-23, showing a relative increase of nearly 40% between -45 and +85°C. Figure 16-24 shows the variation of quiescent current consumption for different frequency settings of the internal RC oscillator. It can be seen that the quiescent current varies by about 20% between 100kHz and 2MHz. © Semtech 2006 > 1. ELCONV NORMALIZED TO 25°C ...

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... Temperature [°C] (a) Figure 16-23. (a) Absolute and (b) relative change inquiescent current consumption vs. temperature © Semtech 2006 800 700 PGA1, 2 & ADC 600 500 PGA1 & ADC 400 PGA1 + ADC 300 200 No PGAs, ADC only 100 2.5 3.0 3 ...

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... Figure 16-25 shows power supply rejection ratio (PSRR and 5V supply voltage, and for various PGA gains. PSRR is defined as the ratio (in dB) of voltage supply change ( the change in the converter output (in V). PSRR depends on both PGA gain and supply voltage V Figure 16-25. Power supply rejection ratio (PSRR) © Semtech 2006 PGA2 PGA1 PGA3 ...

Page 117

... For the lowest noise, set the highest possible gain on the first (front) PGA stage used in the chain. For example application where a gain needed, set the gain of PGA2 to 10, set the gain of PGA3 to 2. © Semtech 2006 GAIN =5 GAIN = 10 GAIN = 20 GAIN =100 ...

Page 118

... Normalized Frequency - f *(OSR/f 1 0.8 0.6 0.4 0 Normalized Frequency - f *(OSR/f Figure 16-26. Frequency response: normalized magnitude vs. frequency for different N © Semtech 2006 . Notice that the frequency axes are normalized to one elementary conversion = − (Hz) for ,..., ( ELCONV = 20.48kHz for OSR = 512. Notice that this S 1 ...

Page 119

... IB_AMP_ADC[1:0]. (This reduces the maximum sampling frequency according to Table 16-26.) 5) Reduce internal RC oscillator frequency and/or sampling frequency. Finally, remember that power reduction is typically traded off with reduced linearity, larger noise and slower maximum sampling speed. © Semtech 2006 . DD 16-33 XE8805/05A www.semtech.com ...

Page 120

... Vmult (Voltage Multiplier) 17.1 Features 17.2 Overview 17.3 Control register 17.4 External component © Semtech 2006 17-1 XE8805/05A 17-2 17-2 17-2 17-2 www.semtech.com ...

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... Table 177-1. RegVmultCfg0 17.4 External component When the multiplier is enabled, a capacitor has to be connected to the VMULT pin. If the multiplier is disabled, the pin may remain floating. Capacitor on VMULT © Semtech 2006 Function enable of the vmult ‘1’ : enabled ‘0’ : disabled system clock division factor ‘ ...

Page 122

... First order low pass filter 18.6.2 Second order low pass filter 18.7 4-20mA loop 18.7.1 2-wire loop with first order filtering 18.7.2 2-wire loop with second order filtering © Semtech 2006 18-1 XE8805/05A 18-2 18-2 18-3 18-4 18-4 18-4 18-5 ...

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... PWM modulation are programmable by writing the codes CodeLmax and NsOrder to the configuration register. The possible noise shaper order is 0 (which means no noise shaping The possible PWM modulation resolution m can be set between 4 and 11. © Semtech 2006 Sigma-delta PWM modulator ...

Page 124

... CodeLmax(2:0) rw 2:1 Enable(1: Fin rw Pos. RegDasCfg1 rw 7 INV rw © Semtech 2006 reset function 0 Data to convert LSB resetsystem Table 18-1. RegDasInLsb reset function 0 Data to convert MSB resetsystem Table 18-2. RegDasInMsb reset function 00 Noise Shaper order resetsystem 00 : order order order 2 000 PWM pulse resolution : ...

Page 125

... Advantages: Using a high order noise shaper together with a PWM modulator with low resolution reduces the ratio between the low pass cut off frequency and the PWM switching frequency for the same total resolution. This can be used to © Semtech 2006 18-4 XE8805/05A ...

Page 126

... In Table 18-5 the required cut-off frequency of the low pass filter is shown for a noise shaper of order function of the desired resolution for both a first and second order low pass filter. The PWM modulation factor m should be chosen equal to the desired resolution. © Semtech 2006 can be calculated as a function of the selected modulation width f ...

Page 127

... Table 18-6. Low pass cut-off frequency as a function of the selected PMW modulation and required resolution for a © Semtech 2006 f for LpOrder=1 (Hz) c 7812 1953 488 122 30 7.6 1.9 0.48 NsOrder=00, f =2MHz). RC ⎛ ...

Page 128

... Note that the amplifier can not be used to generate signals that are larger than the supply voltages VBAT and VSS since the amplifier inputs and outputs are clamped to these voltages. The amplifier inputs and outputs should stay within the input and output ranges specified below. © Semtech 2006 5 6 ...

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... Figure 18-2 shows a possible implementation of a first order low pass filter. Ideally, the analog ground should be halfway between VBAT and VSS. The gain G and cut-off frequency π example, to obtain a 1kHz filter with unity gain, we can choose C=1nF and R1=R2=150kΩ. © Semtech 2006 min typ max 80 100 250 450 200 VSS-0.2 VBAT-1 ...

Page 130

... A 60Hz unity gain low pass Butterworth filter can be built choosing R=180kΩ, C=12nF, k=1, m=0.183, n=8.33. Note that parasitic capacitors between the DAS_OUT node and the filter output DAS_AO will adversely affect the high frequency behavior of the filter. Care should be taken when routing these signals. © Semtech 2006 DAS_OUT R ...

Page 131

... D/A corresponds to 4mA. The amplifier will force a current through the bipolar transistor so that the voltage on the filter V and VSS =(VSS-V -)/R . loop EXT sense © Semtech 2006 DAS_OUT R nR DAS_AI_M mC DAS_AO amp DAS_AI_P analog ground Figure 18-3. Second order low pass filter. ...

Page 132

... D/A code is 0: offset − ⋅ ( VBAT VSS ) R ≤ ⋅ offset sense © Semtech 2006 is then chosen much larger depending on the current error requirement /0.001. f2 sense VBAT VBAT R offset DAS_OUT A R DAS_AI_P V DAS_AO amp ...

Page 133

... For this schematic, all the equations of the first order schematic remain valid. The values of R calculated from the cut-off frequency π For the 1kHz example, we can chose R © Semtech 2006 =50Ω, V =30V and a 1kHz low pass filter, we can use: sense EXT =100kΩ, R =2.4MΩ, C =1.8nF. f2 offset f +R has to be chosen the same way as R ...

Page 134

... XE88xx VBAT Sensor VSS Figure 18-6. 2-wire 4-20mA with second order filter and increased stability © Semtech 2006 VBAT R offset R f1 DAS_OUT A V DAS_AI_P DAS_AO amp C fs DAS_AI_M R fs VSS C f 18-13 XE8805/05A 4-20mA Voltage regulator V + EXT R lim2 f R lim1 sense ...

Page 135

... Features 19.2 General description 19.3 Register map 19.4 D/A specification 19.5 Amplifier specification 19.6 Application examples 19.6.1 Voltage controlled sensor bias 19.6.2 Current controlled sensor bias © Semtech 2006 19-1 XE8805/05A 19-2 19-2 19-2 19-3 19-3 19-4 19-4 19-4 www.semtech.com ...

Page 136

... An amplifier is added that can be used to drive the large sensor currents. 19.3 Register map The bias D/A has two registers. Pos. RegDabIn rw 7-0 DabIn(7:0) rw Pos. RegDabCfg rw 7-2 r 1-0 Enable(1:0) rw © Semtech 2006 V BATT amp MOS V SS Figure 19-1. General block diagram reset function 0 Data to convert resetsystem Table 19-1. RegDabIn reset function 0 ...

Page 137

... I max source current source PSRR power supply rejection ratio I quiescent bias current bias I off current off 1. For all possible combinations of resistive load and capacitive load DC. © Semtech 2006 min typ max 8 0.25 1 DAB_R_M DAB_R_P VSS+2.3 VBAT VSS VBAT-2.3 1.6 on DAB_OUT smaller than 100pF ...

Page 138

... AOM 19.6.2 Current controlled sensor bias Figure 19-3 shows the principle of a current controlled sensor bias schematic. In this case, the amplifier forces the voltage equal to the D/A output voltage V R © Semtech 2006 V refp VBAT or a Reference voltage source DAB_R_P V refn ...

Page 139

... VR sensor current is now: − refn sensor R R sense sense In this case recommended to choose V voltage on the sensor. The only limit is now V © Semtech 2006 − ⋅ − code 255 = refp refn R sense and the sensor impedance. ...

Page 140

... XE8805A this configuration, the bridge current and DAB_AOM increase when DAB_OUT increases Figure 19-4. Current controlled sensor bias. . © Semtech 2006 V VBAT refp or another reference voltage DAB_R_P V DAB_R_M refn VSS V DAB_OUT D/A DAB_AIP DAB_AOP amp V sensor DAB_AOM DAB_AIM 19-6 XE8805/05A Vrefp must remain above VSS + 2.3 V VBAT Ω ...

Page 141

... Block schematic 20.6 General counter registers operation 20.7 Clock selection 20.8 Counter mode selection 20.9 Counter / Timer mode 20.10 PWM mode 20.11 Capture function © Semtech 2006 20-1 XE8805/05A 20-2 20-2 20-2 20-3 20-4 20-4 20-5 20-5 20-6 20-8 20-9 ...

Page 142

... Note: When writing to RegCntA or RegCntB, the processor writes the counter comparison values. When reading these locations, the processor reads back either the actual counter value or the last captured value if the capture mode is active. bit RegCntC 7-0 CounterC 7-0 CounterC © Semtech 2006 rw reset r xxxxxxxx w xxxxxxxx Table 20-1. RegCntA rw ...

Page 143

... CapFunc(1:0) 3-2 Pwm1Size(1:0) 1-0 Pwm0Size(1:0) RegCntOn bit 7 CntDEnable 2 CntCEnable 1 CntBEnable 0 CntAEnable 20.4 Interrupts and events map Interrupt source IrqA IrqB IrqC IrqD © Semtech 2006 rw reset r xxxxxxxx w xxxxxxxx Table 20-4. RegCntD rw reset Table 20-5. RegCntCtrlCk rw Reset rw x Counter down counting (0=down) ...

Page 144

... For a correct acquisition of the counter value, use one of the three following methods: 1) Stop the concerned counter, perform the read operation and restart the counter. While stopped, the counter content is frozen and the counter does not take into account the clock edges delivered on the external pin. © Semtech 2006 ck1k ck32k Counter A ...

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... For all counter modes, the source of the down or upcount selection is given (either the bit CntADownUp or the bit CntBDownUp). Also, the mapping of the interrupt sources IrqA and IrqB and the PWM output on PB(0) in these different modes is shown. © Semtech 2006 Clock source for CounterA ...

Page 146

... RegCntConfig1 or in downcount mode by resetting this bit. Counters A and B can be cascaded to behave bit counter by setting CascadeAB in the RegCntConfig1 register. Counters C and D can be cascaded by setting CascadeCD. When cascaded, the up/down count modes of the counters B and D are defined respectively by the up/down count modes set for the counters A and C. © Semtech 2006 Counter A Counter B IrqA ...

Page 147

... This interrupt is additional to the interrupt which has already been generated when the counter reached the zero or the target value. dow n counting clock counter X RegcntX_r XX RegCntX_w XX write RegCntX CntXDownUp IrqX CntXEnable up counting clock counter X RegCntX_r XX 0 RegCntX_w XX write RegCntX CntXDownUp IrqX CntXEnable Figure 20-2. Up and down count interrupt generation. © Semtech 2006 20-7 XE8805/05A ...

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... PWM output which is always tied to 1. PwmXsize(1:0) Table 20-13: Resolution selection in cascaded PWM mode Small PWM code Large PWM code The period of the PWM signal is given by the formula: © Semtech 2006 Resolution 11 16 bits 10 14 bits ...

Page 149

... Due to the synchronization mechanism of the shadow registers and depending on the frequency ratio between the capture and counter clocks, the interrupts may be generated one or only two counter clock pulses after the effective capture condition occurred. When the counters A and B are not cascaded and do not operate on the © Semtech 2006 Th DCR = Tper − ...

Page 150

... It must be noted that when counters A and B are cascaded, the capture might happen at different cycles for the A and B registers. This is due to the asynchronous relationship between counter and capture clock and to the fact that the capture condition detection is independent for A and B counters. © Semtech 2006 20-10 XE8805/05A ...

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... VLD (Voltage Level Detector) 21.1 Features 21.2 Overview 21.3 Register map 21.4 Interrupt map 21.5 VLD operation © Semtech 2006 21-1 XE8805/05A 21-2 21-2 21-2 21-2 21-2 www.semtech.com ...

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... The VLD is controlled by VldRange, VldTune and VldEn. VldRange selects the voltage range to be detected, while VldTune is used to fine-tune this voltage level in 8 steps. VldEn is used to enable (disable) the VLD with a 1(0) value respectively. Disabled, the block will dissipate no power. © Semtech 2006 reset function 0000 ...

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... VLD is enabled, a maskable interrupt request is sent if the voltage level falls below the threshold. One can also poll the VLD and monitor the actual measurement result by reading the VldResult bit of the RegVldStat. This result is only valid as long as the VldValid bit is ‘1’. An interrupt is generated on each rising edge of VldResult. © Semtech 2006 min typ max Note 1 1 ...

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... Physical Dimensions 22.1 QFP type package © Semtech 2006 22-1 XE8805/05A 22-2 www.semtech.com ...

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... The QFP package dimensions are given in Figure 22-1 and Table 22-1. The dimensions conform to JEDEC MS- 026 Rev. C. Figure 22-1. QFP type package package 10.0 12.0 1.4 LQFP-64 Table 22-1. QFP package dimensions © Semtech 2006 0.10 0.22 0.5 22-2 XE8805/05A www.semtech.com ...

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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech. assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range ...

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