XE8805AMI028LF Semtech, XE8805AMI028LF Datasheet - Page 22

• Manufacturer Part Number: XE8805AMI028LF
• Description: IC DAS 16BIT FLASH 8K MTP 64LQFP
• Manufacturer: Semtech

Specifications of XE8805AMI028LF

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (22 kB)
• Controller Series: XE8000
• Ram Size: 512 x 8
• Interface: UART, USRT
• Number Of I /o: 24
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Supply Voltage Range: 2.4V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dec
Dec reg,
Decc reg1,
Decc
Decc reg,
And reg,#data[7:0]
And reg1, reg2,
And reg1,
And reg,
Or reg,#data[7:0]
Or reg1, reg2,
Or reg1,
Or reg,
Xor reg,#data[7:0]
Xor reg1, reg2,
Xor reg1,
Xor reg,
Add reg,#data[7:0]
Add reg1, reg2,
Add reg1,
Add reg,
Addc reg,#data[7:0]
Addc reg1, reg2,
Addc reg1,
Addc reg,
Subd reg,#data[7:0]
Subd reg1, reg2,
Subd reg1,
Subd reg,
Subdc reg,#data[7:0]
Subdc reg1, reg2,
Subdc reg1,
Subdc reg,
Subs reg,#data[7:0]
Subs reg1, reg2,
Subs reg1,
Subs reg,
Subsc reg,#data[7:0]
Subsc reg1, reg2,
Subsc reg1,
Subsc reg,
Mul reg,#data[7:0]
Mul reg1, reg2,
Mul reg1,
Mul reg,
Mula reg,#data[7:0]
Mula reg1, reg2,
Mula reg1,
Mula reg,
Mshl reg,#shift[2:0]
Mshr reg,#shift[2:0]
Mshra reg,#shift[2:0]
Cmp reg,#data[7:0]
Cmp reg1,
Cmp reg,
Cmpa reg,#data[7:0]
Cmpa reg1,
Cmpa reg,
Tstb reg,#bit[2:0]
Setb reg,#bit[2:0]
Clrb reg,#bit[2:0]
Invb reg,#bit[2:0]
© Semtech 2006
reg
reg
eaddr
reg2
eaddr
eaddr
eaddr
eaddr
eaddr
eaddr
reg2
reg2
eaddr
eaddr
reg2
reg2
eaddr
eaddr
eaddr
reg2
eaddr
reg2
reg2
reg2
reg2
eaddr
reg2
eaddr
reg2
reg2
reg2
reg3
reg3
reg3
reg3
reg3
reg3
reg3
reg3
reg3
reg3
reg3
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a
u, u, u, a*
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
-, -, Z, a
-, -, Z, a
-, -, Z, a
-, -, Z, a
-,-, Z, a
a := reg-1; if a=hFF then C := 0 else C := 1;
a := DM(eaddr)-1; if a=hFF then C := 0 else C := 1;
a := reg2-(1-C); if a=hFF and C=0 then C := 0 else C := 1;
a := reg-(1-C); if a=hFF and C=0 then C := 0 else C := 1;
a := DM(eaddr)-(1-C); if a=hFF and C=0 then C := 0 else C := 1;
a :=
a :=
a :=
a :=
a :=
a :=
a :=
a :=
a :=
a :=
a :=
a :=
a := reg+data[7:0]; if overflow then C:=1 else C := 0;
a := reg2+reg3; if overflow then C:=1 else C := 0;
a := reg1+reg2; if overflow then C:=1 else C := 0;
a := reg+DM(eaddr); if overflow then C:=1 else C := 0;
a := reg+data[7:0]+C; if overflow then C:=1 else C := 0;
a := reg2+reg3+C; if overflow then C:=1 else C := 0;
a := reg1+reg2+C; if overflow then C:=1 else C := 0;
a := reg+DM(eaddr)+C; if overflow then C:=1 else C := 0;
a := data[7:0]-reg; if underflow then C := 0 else C := 1;
a := reg2-reg3; if underflow then C := 0 else C := 1;
a := reg2-reg1; if underflow then C := 0 else C := 1;
a := DM(eaddr)-reg; if underflow then C := 0 else C := 1;
a := data[7:0]-reg-(1-C); if underflow then C := 0 else C := 1;
a := reg2-reg3-(1-C); if underflow then C := 0 else C := 1;
a := reg2-reg1-(1-C); if underflow then C := 0 else C := 1;
a := DM(eaddr)-reg-(1-C); if underflow then C := 0 else C := 1;
a := reg-data[7:0]; if underflow then C := 0 else C := 1;
a := reg3-reg2; if underflow then C := 0 else C := 1;
a := reg1-reg2; if underflow then C := 0 else C := 1;
a := reg-DM(eaddr); if underflow then C := 0 else C := 1;
a := reg-data[7:0]-(1-C); if underflow then C := 0 else C := 1;
a := reg3-reg2-(1-C); if underflow then C := 0 else C := 1;
a := reg1-reg2-(1-C); if underflow then C := 0 else C := 1;
a := reg-DM(eaddr)-(1-C); if underflow then C := 0 else C := 1;
a := (data[7:0]*reg)[7:0];
a := (reg2*reg3)[7:0];
a := (reg2*reg1)[7:0];
a := (DM(eaddr)*reg)[7:0];
a := (data[7:0]*reg)[7:0];
a := (reg2*reg3)[7:0];
a := (reg2*reg1)[7:0];
a := (DM(eaddr)*reg)[7:0];
a := (reg*2
a := (reg*2
a := (reg*2
a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z)
a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z)
a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z)
a[bit] := reg[bit]; other bits in a are 0
reg[bit]
reg[bit]
reg[bit]
reg
reg2
reg1
reg
reg
reg2
reg1
reg
reg
reg2
reg1
reg
:= 1; other bits unchanged; a :=
:= 0; other bits unchanged; a :=
:= not reg[bit]; other bits unchanged; a :=
and data[7:0];
and DM(eaddr);
or data[7:0];
or DM(eaddr);
xor data[7:0];
or DM(eaddr);
and reg3;
and reg2;
or reg3;
or reg2;
xor reg3;
xor reg2;
shift
(8-shift
(8-shift
)[7:0];
)[7:0];
)[7:0];
reg1
reg1
reg1
reg1
reg
reg1
reg1
3-5
reg
reg
reg
reg1
reg1
reg1
reg1
reg
reg
:= a
:= a
reg
reg
:= (reg*2
:= a
:= a
reg
reg
reg
:= a
:= a
:= a
:= (reg*2
:= (reg*2
:= a
:= a
:= (reg2*reg3)[15:8]
:= (reg2*reg1)[15:8]
reg
:= (reg2*reg3)[15:8]
:= (reg2*reg1)[15:8]
reg
:= a
:= a
:= (data[7:0]*reg)[15:8]
:= (data[7:0]*reg)[15:8]
:= a
:= (DM(eaddr)*reg)[15:8]
:= (DM(eaddr)*reg)[15:8]
shift
(8-shift
(8-shift
)[15:8]
)[15:8]
)[15:8]
reg
reg
reg
:= a
reg
reg1
reg1
reg
reg1
reg1
reg1
reg1
reg
reg1
reg1
reg
reg
reg
:= a
:= a
:= a
reg
:= a
reg
reg
:= a
:= a
:= a
:= a
reg
reg
reg1
reg1
reg1
reg1
:= a
:= a
reg1
:= a
:= a
:= a
:= a
:= a
reg
:= a
reg
:= a
:= a
:= a
:= a
reg
:= a
:= a
reg
:= a
:= a
:= a
reg
:= a
:= a
XE8805/05A
:= a
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