XE8805AMI028LF Semtech, XE8805AMI028LF Datasheet - Page 99

• Manufacturer Part Number: XE8805AMI028LF
• Description: IC DAS 16BIT FLASH 8K MTP 64LQFP
• Manufacturer: Semtech

Specifications of XE8805AMI028LF

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (22 kB)
• Controller Series: XE8000
• Ram Size: 512 x 8
• Interface: UART, USRT
• Number Of I /o: 24
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Supply Voltage Range: 2.4V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Finally, combining equations Eq. 5 to Eq. 7 for the three PGA stages, the input voltage V
to V
where the total PGA gain is defined as:
and the total PGA offset is:
16.7 ADC Characteristics
The main performance characteristics of the ADC (resolution, conversion time, etc.) are determined by three
programmable parameters:
The setting of these parameters and the resulting performances are described hereafter.
16.7.1
A conversion is started each time the bit START or the bit DEF is set. As depicted in Figure 16-5, a complete
analog-to-digital conversion sequence is made of a set of N
quantization step. Each elementary conversion is made of (OSR+1) sampling periods T
The result is the mean of the elementary conversion results. An important feature is that the elementary
conversions are alternatively performed with the offset of the internal amplifiers contributing in one direction and the
other to the output code. Thus, converter internal offset is eliminated if at least two elementary sequences are
performed (i.e. if N
properly.
© Semtech 2006
•
•
•
IN
by:
sampling frequency f
over-sampling ratio OSR, and
number of elementary conversions N
V
GD
GDoff
T
ELCONV
IN
Conversion Sequence
,
TOT
ADC
TOT
=
Conversion index
=
=
(
GD
GD
OSR
=
GDoff
ELCONV
3
TOT
⋅
+
GD
1
Init
⋅
/ )
V
Offset
3
2
IN
f
≥ 2). A few additional clock cycles are also required to initiate and end the conversion
+
⋅
S
GD
−
GD
Conversion
Elementary
S
GDoff
,
1
3
(s)
⋅
1
+
Figure 16-5. Analog-to-digital conversion sequence
GDoff
TOT
⋅
V
T
2
(V/V)
ELCONV
REF
Conversion
Elementary
(V)
ELCONV
= (OSR+1)/f
2
-
(V/V)
.
T
S
CONV
16-13
Conversion
Elementary
N
ELCONV
ELCONV
+
- 1
elementary incremental conversions and a final
(Eq. 9)
(Eq. 10)
(Eq. 11)
(Eq. 12)
Conversion
Elementary
N
ELCONV
-
End
S
=1/f
IN,ADC
Conversion
S
Result
, i.e.:
XE8805/05A
of the ADC is related
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