XE8805AMI028LF Semtech, XE8805AMI028LF Datasheet - Page 117

• Manufacturer Part Number: XE8805AMI028LF
• Description: IC DAS 16BIT FLASH 8K MTP 64LQFP
• Manufacturer: Semtech

Specifications of XE8805AMI028LF

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (22 kB)
• Controller Series: XE8000
• Ram Size: 512 x 8
• Interface: UART, USRT
• Number Of I /o: 24
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Supply Voltage Range: 2.4V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.9 Application Hints
16.9.1
The PGAs of the acquisition chain employ switched-capacitor techniques. For this reason, while a conversion is
done, the input impedance on the selected channel of the PGAs is inversely proportional to the sampling frequency
f
The input impedance observed is the input impedance of the first PGA stage that is enabled or the input
impedance of the ADC if all three stages are disabled.
PGA1 (with a gain of 10), PGA2 (with a gain of 10) and PGA3 (with a gain of 10) each have a minimum input
impedance of 150kΩ at f
reducing the gain and/or by reducing the sampling frequency. Therefor, with a gain of 1 and a sampling frequency
of 100kHz, Z
The input impedance on channels that are not selected is very high (>100MΩ).
16.9.2
PGAs are reset after each writing operation to registers RegAcCfg1-5. Similarly, input channels are switched after
modifications of AMUX[4:0] or VMUX. To ensure precise conversion, the ADC must be started after a PGA or
inputs common-mode stabilization delay. This is done by writing bit START several cycles after PGA settings
modification or channel switching. Delay between PGA start or input channel switching and ADC start should be
equivalent to OSR (between 8 and 1024) number of cycles. This delay does not apply to conversions made without
the PGAs.
If the ADC is not settled within the specified period, there is most probably an input impedance problem (see
previous section).
16.9.3
Hereafter are a few design guidelines that should be taken into account when using the ZoomingADC™:
© Semtech 2006
S
and to stage gain as given in equation 22.
1)
2)
3)
4)
Z
Keep in mind that increasing the overall PGA gain, or "zooming" coefficient, improves linearity but
degrades noise performance.
Use the minimum number of PGA stages necessary to produce the desired gain ("zooming") and offset.
Bypass unnecessary PGAs.
For high gains (>50), use PGA stage 1. For low gains (<50) use stages 2 and 3.
For the lowest noise, set the highest possible gain on the first (front) PGA stage used in the chain. For
example, in an application where a gain of 20 is needed, set the gain of PGA2 to 10, set the gain of PGA3
to 2.
in
Input Impedance
PGA Settling or Input Channel Modifications
PGA Gain & Offset, Linearity and Noise
≥
in
V
V
> 7.6MΩ.
768
Supply
DD
DD
f
= 5V
= 3V
s
⋅
10
⋅
gain
9
Ω
GAIN = 1
Hz
S
Table 16-29. PSRR (n = 16 bits, V
79
72
= 512kHz (see Specification Table). Larger input impedance can be obtained by
(Eq. 22)
GAIN =5
78
79
GAIN = 10
100
90
16-31
GAIN = 20
IN
99
90
= V
REF
= 2.5V, f
GAIN =100
97
86
S
= 500kHz)
Unit
dB
dB
XE8805/05A
www.semtech.com