XE8805AMI028LF Semtech, XE8805AMI028LF Datasheet - Page 78

• Manufacturer Part Number: XE8805AMI028LF
• Description: IC DAS 16BIT FLASH 8K MTP 64LQFP
• Manufacturer: Semtech

Specifications of XE8805AMI028LF

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (22 kB)
• Controller Series: XE8000
• Ram Size: 512 x 8
• Interface: UART, USRT
• Number Of I /o: 24
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Supply Voltage Range: 2.4V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The word length (7 or 8 data bits) can be chosen with UartWL. A parity bit is added during transmission or checked
during reception if UartPE is set. The parity mode (odd or even) can be chosen with UartPM.
Setting the bits UartXRx and UartXTx inverts the Rx respectively Tx signals.
The bit UartEcho is used to send the received data automatically back. The transmission function becomes then:
Tx = Rx XOR UartXTx.
14.6.2
In order to send data, the transmitter has to be enabled by setting the bit UartEnTx. Data to be sent has to be
written to the register RegUartTx. The bit UartTxFull in RegUartTxSta then goes to 1, indicating to the transmitter
that a new word is available. As soon as the transmitter has finished sending the previous word, it then loads the
contents of the register RegUartTx to an internal shift register and clears the UartTxFull bit. An interrupt is
generated on Irq_uart_Tx at the falling edge of the UartTxFull bit. The bit UartTxBusy in RegUartTxSta shows
that the transmitter is busy transmitting a word.
A timing diagram is shown in Figure 14-1. Data are first sent LSB.
New data should be written to the register RegUartTx only while UartTxFull is 0, otherwise data will be lost.
Figure 14-1. Uart transmission timing diagram.
14.6.3
On detection of the start bit, the UartRxBusy bit is set. On detection of the stop bit, the received data are
transferred from the internal shift register to the register RegUartRx. At the same time, the UartRxFull bit is set
© Semtech 2006
Asynchronous Transmission
Asynchronous Transmission (back to back)
write to RegUartTx
write to RegUartTx
reguarttx_shift
reguarttx_shift
UartTxBusy
UartTxBusy
RegUartTx
Irq_uart_Tx
RegUartTx
Irq_uart_Tx
UartTxFull
UartTxFull
shift clock
shift clock
Transmission
Reception
Tx
Tx
word 1
word 1
word 1
start
word 2
word 1
start
word 2
word 1
b0
b0
14-5
b1
b6/7
stop
b6/7
word 2
start
parity
stop
XE8805/05A
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