XE8805AMI028LF Semtech, XE8805AMI028LF Datasheet - Page 149

• Manufacturer Part Number: XE8805AMI028LF
• Description: IC DAS 16BIT FLASH 8K MTP 64LQFP
• Manufacturer: Semtech

Specifications of XE8805AMI028LF

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (22 kB)
• Controller Series: XE8000
• Ram Size: 512 x 8
• Interface: UART, USRT
• Number Of I /o: 24
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Supply Voltage Range: 2.4V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The duty cycle ratio DCR of the PWM signal is defined as:
DCR can be selected between 0 % and
DCR in % in function of the RegCntX content(s) is given by the relation:
20.11 Capture function
The 16-bit capture register is provided to facilitate frequency measurements. It provides a safe reading mechanism
for the counters A and B when they are running. When the capture function is active, the processor does not read
anymore the counters A and B directly, but instead reads shadow registers located in the capture block. An
interrupt is generated after a capture condition has been met when the shadow register content is updated. The
capture condition is user defined by selecting either internal capture signal sources derived from the prescaler or
from the external PA(2) or PA(3) ports. Both counters use the same capture condition.
When the capture function is active, the A and B counters must be written with the value 0xFF and can either
upcount or downcount. They do count circularly: they restart at zero or at the maximal value (either 0xFF when not
cascaded or 0xFFFF when cascaded) when respectively an overflow or an underflow condition occurs in the
counting.
CapFunc(1:0) in register RegCntConfig2 determines if the capture function is enabled or not and selects which
edges of the capture signal source are valid for the capture operation. The source of the capture signal can be
selected by setting CapSel(1:0) in the RegCntConfig2 register. For all sources, rising, falling or both edge
sensitivity can be selected. Table 20-14 shows the capture condition as a function of the setting of these
configuration bits.
CapFunc(1:0) and CapSel(1:0) can be modified only when the counters are stopped otherwise data may be
corrupted during one counter clock cycle.
Due to the synchronization mechanism of the shadow registers and depending on the frequency ratio between the
capture and counter clocks, the interrupts may be generated one or only two counter clock pulses after the
effective capture condition occurred. When the counters A and B are not cascaded and do not operate on the
© Semtech 2006
CapSel(1:0)
11
10
01
00
Selected capture signal
32 K
PA3
PA2
1 K
Table 20-14: Capture condition selection
2
resolution
2
resolution
DCR
−
DCR =
=
1
CapFunc
*
100
100
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
20-9
2
*
Tper
resolution
RegCntX
%.
Th
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Capture disabled
Rising edge
Falling edge
Both edges
Selected condition
-
1 K rising edge
1 K falling edge
1 K both edges
-
32 K rising edge
32 K falling edge
32 K both edges
-
PA3 rising edge
PA3 falling edge
PA3 both edges
-
PA2 rising edge
PA2 falling edge
PA2 both edges
Capture condition
XE8805/05A
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