PIC16F887-I/PT Microchip Technology Inc., PIC16F887-I/PT Datasheet - Page 154

• Manufacturer Part Number: PIC16F887-I/PT
• Description: MCU, 8-Bit, 8KW Flash, 368 RAM, 36 I/O, TQFP-44
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F887-I/PT

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 35
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TFQP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: MSSP or EUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F822/883/884/886/887
12.1.1.4
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
12.1.1.5
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set the
EUSART will shift 9 bits out for each character transmit-
ted. The TX9D bit of the TXSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the 8 Least Significant bits into the TXREG. All nine bits
of data will be transferred to the TSR shift register
immediately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 12.1.2.7 “Address
Detection” for more information on the Address mode.
FIGURE 12-3:
FIGURE 12-4:
DS41291D-page 152
RC4/C2OUT/TX/CK
(Interrupt Reg. Flag)
RC4/C2OUT/TX/CK
Note:
Reg. Empty Flag)
Reg. Empty Flag)
Note:
Reg. Empty Flag)
Write to TXREG
(Transmit Buffer
Write to TXREG
(Transmit Shift
(Transmit Shift
BRG Output
(Shift Clock)
BRG Output
(Shift Clock)
TRMT bit
TRMT bit
TXIF bit
TXIF bit
The TSR register is not mapped in data
memory, so it is not available to the user.
This timing diagram shows two consecutive transmissions.
TSR Status
Transmitting 9-Bit Characters
pin
pin
ASYNCHRONOUS TRANSMISSION
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
1 T
Word 1
Transmit Shift Reg
CY
Word 1
Transmit Shift Reg.
Word 1
Word 1
1 T
CY
Start bit
Start bit
Word 2
1 T
CY
bit 0
bit 0
Preliminary
bit 1
Word 1
bit 1
Word 1
12.1.1.6
1.
2.
3.
4.
5.
6.
7.
Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 12.3 “EUSART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If 9-bit transmission is desired, set the TX9 con-
trol bit. A set ninth data bit will indicate that the 8
Least Significant data bits are an address when
the receiver is set for address detection.
Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
If interrupts are desired, set the TXIE interrupt
enable bit. An interrupt will occur immediately
provided that the GIE and PEIE bits of the
INTCON register are also set.
If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
Load 8-bit data into the TXREG register. This
will start the transmission.
Asynchronous Transmission Set-up:
bit 7/8
bit 7/8
Word 2
Transmit Shift Reg.
© 2007 Microchip Technology Inc.
Stop bit
Stop bit
Start bit
Word 2
bit 0