PIC16F887-I/PT Microchip Technology Inc., PIC16F887-I/PT Datasheet - Page 199

• Manufacturer Part Number: PIC16F887-I/PT
• Description: MCU, 8-Bit, 8KW Flash, 368 RAM, 36 I/O, TQFP-44
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F887-I/PT

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 35
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TFQP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: MSSP or EUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.4.10
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN (SSPCON2
register). When this bit is set, the SCL pin is pulled low
and the contents of the Acknowledge Data bit (ACKDT)
is presented on the SDA pin. If the user wishes to gener-
ate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
the SCL pin is de-asserted (pulled high). When the SCL
pin is sampled high (clock arbitration), the Baud Rate
Generator counts for T
low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 13-17).
13.4.10.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 13-17:
© 2007 Microchip Technology Inc.
Note: T
ACKNOWLEDGE SEQUENCE TIMING
WCOL Status Flag
SSPIF
BRG
Acknowledge sequence starts here,
SDA
SCL
= one Baud Rate Generator period.
BRG
ACKNOWLEDGE SEQUENCE WAVEFORM
Set SSPIF at the end
of receive
. The SCL pin is then pulled
ACKEN = 1, ACKDT = 0
Write to SSPCON2
8
D0
BRG
PIC16F882/883/884/886/887
) and
Preliminary
Cleared in
software
T
BRG
ACK
13.4.11
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2 register). At the end of a
receive/transmit, the SCL line is held low after the fall-
ing edge of the ninth clock. When the PEN bit is set, the
master will assert the SDA line low. When the SDA line
is sampled low, the Baud Rate Generator is reloaded
and counts down to 0. When the Baud Rate Generator
times out, the SCL pin will be brought high, and one
T
SDA pin will be de-asserted. When the SDA pin is sam-
pled high while SCL is high, the P bit (SSPSTAT regis-
ter) is set. A T
SSPIF bit is set (Figure 13-18).
13.4.11.1
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
BRG
T
BRG
9
(Baud Rate Generator rollover count) later, the
Set SSPIF at the end
of Acknowledge sequence
STOP CONDITION TIMING
WCOL Status Flag
BRG
ACKEN automatically cleared
later, the PEN bit is cleared and the
Cleared in
software
DS41291D-page 197