PIC16F887-I/PT Microchip Technology Inc., PIC16F887-I/PT Datasheet - Page 35

• Manufacturer Part Number: PIC16F887-I/PT
• Description: MCU, 8-Bit, 8KW Flash, 368 RAM, 36 I/O, TQFP-44
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F887-I/PT

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 35
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TFQP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: MSSP or EUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.2.2.5
The PIE2 register contains the interrupt enable bits, as
shown in Register 2-5.
REGISTER 2-5:
© 2007 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OSFIE
R/W-0
PIE2 Register
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables oscillator fail interrupt
0 = Disables oscillator fail interrupt
C2IE: Comparator C2 Interrupt Enable bit
1 = Enables Comparator C2 interrupt
0 = Disables Comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1 = Enables Comparator C1 interrupt
0 = Disables Comparator C1 interrupt
EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enables EEPROM write operation interrupt
0 = Disables EEPROM write operation interrupt
BCLIE: Bus Collision Interrupt Enable bit
1 = Enables Bus Collision interrupt
0 = Disables Bus Collision interrupt
ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable bit
1 = Enables Ultra Low-Power Wake-up interrupt
0 = Disables Ultra Low-Power Wake-up interrupt
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables CCP2 interrupt
0 = Disables CCP2 interrupt
R/W-0
C2IE
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
W = Writable bit
‘1’ = Bit is set
R/W-0
C1IE
PIC16F882/883/884/886/887
R/W-0
EEIE
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
BCLIE
R/W-0
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
ULPWUIE
R/W-0
x = Bit is unknown
U-0
—
DS41291D-page 33
CCP2IE
R/W-0
bit 0