PIC16F887-I/PT Microchip Technology Inc., PIC16F887-I/PT Datasheet - Page 224

• Manufacturer Part Number: PIC16F887-I/PT
• Description: MCU, 8-Bit, 8KW Flash, 368 RAM, 36 I/O, TQFP-44
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F887-I/PT

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 35
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TFQP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: MSSP or EUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F882/883/884/886/887
14.6
The Power-down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running.
• PD bit in the STATUS register is cleared.
• TO bit is set.
• Oscillator driver is turned off.
• I/O ports maintain the status they had before
For lowest current consumption in this mode, all I/O pins
should be either at V
drawing current from the I/O pin and the comparators
and CV
impedance inputs should be pulled high or low externally
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at V
current consumption. The contribution from on-chip pull-
ups on PORTA should be considered.
The MCLR pin must be at a logic high level.
14.6.1
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
The first event will cause a device Reset. The two latter
events are considered a continuation of program exe-
cution. The TO and PD bits in the STATUS register can
be used to determine the cause of device Reset. The
PD bit, which is set on power-up, is cleared when Sleep
is invoked. TO bit is cleared if WDT Wake-up occurred.
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
4.
5.
6.
7.
8.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
DS41291D-page 222
SLEEP was executed (driving high, low or high-
impedance).
Note:
External Reset input on MCLR pin.
Watchdog Timer Wake-up (if WDT was enabled).
Interrupt from RB0/INT pin, PORTB change or a
peripheral interrupt.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
ECCP Capture mode interrupt.
A/D conversion (when A/D clock source is FRC).
EEPROM write operation completion.
Comparator output changes state.
Interrupt-on-change.
External Interrupt from INT pin.
EUSART Break detect, I
REF
Power-Down Mode (Sleep)
It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
WAKE-UP FROM SLEEP
should be disabled. I/O pins that are high-
DD
or V
SS
2
, with no external circuitry
C slave.
DD
or V
SS
for lowest
Preliminary
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction, then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
14.6.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
• If the interrupt occurs during or after the execu-
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
Note:
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
tion of a SLEEP instruction, the device will imme-
diately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set and the PD bit will be cleared.
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the corresponding
interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEP instruction is completely executed.
WAKE-UP USING INTERRUPTS
© 2007 Microchip Technology Inc.