PIC16F887-I/PT Microchip Technology Inc., PIC16F887-I/PT Datasheet - Page 195

• Manufacturer Part Number: PIC16F887-I/PT
• Description: MCU, 8-Bit, 8KW Flash, 368 RAM, 36 I/O, TQFP-44
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F887-I/PT

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 35
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TFQP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: MSSP or EUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.4.7
A Repeated Start condition occurs when the RSEN bit
(SSPCON2 register) is programmed high and the I
Logic module is in the Idle state. When the RSEN bit is
set, the SCL pin is asserted low. When the SCL pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPADD<5:0> and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (T
Generator times out, if SDA is sampled high, the SCL
pin will be de-asserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPADD<6:0> and begins count-
ing. SDA and SCL must be sampled high for one T
This action is then followed by assertion of the SDA pin
(SDA = 0) for one T
this, the RSEN bit (SSPCON2 register) will be automat-
ically cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT register) will be set. The SSPIF bit
will not be set until the Baud Rate Generator has timed
out.
FIGURE 13-14:
© 2007 Microchip Technology Inc.
I
START CONDITION TIMING
Falling edge of ninth clock
2
C™ MASTER MODE REPEATED
SDA
SCL
BRG
REPEAT START CONDITION WAVEFORM
, while SCL is high. Following
End of Xmit
BRG
). When the Baud Rate
Write to SSPCON2
occurs here,
SDA = 1,
SCL (no change)
PIC16F882/883/884/886/887
BRG
Preliminary
T
2
SDA = 1,
SCL = 1
C
BRG
.
T
BRG
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
13.4.7.1
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
Note:
Note 1: If RSEN is programmed while any other
Sr = Repeated Start
T
BRG
2: A bus collision during the Repeated Start
At completion of Start bit,
hardware clear RSEN bit
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
Set S (SSPSTAT<3>)
event is in progress, it will not take effect.
condition occurs if:
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
and set SSPIF
WCOL Status Flag
Write to SSPBUF occurs here
from low-to-high.
asserted low. This may indicate that
another master is attempting to
transmit a data “1”.
T
BRG
1st bit
T
BRG
DS41291D-page 193