PIC16F887-I/PT Microchip Technology Inc., PIC16F887-I/PT Datasheet - Page 202

• Manufacturer Part Number: PIC16F887-I/PT
• Description: MCU, 8-Bit, 8KW Flash, 368 RAM, 36 I/O, TQFP-44
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F887-I/PT

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 35
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TFQP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: MSSP or EUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F882/883/884/886/887
13.4.16.1
During a Start condition, a bus collision occurs if:
a)
b)
During a Start condition, both the SDA and the SCL
pins are monitored, if:
the SDA pin is already low,
or the SCL pin is already low,
then:
The Start condition begins with the SDA and SCL pins
de-asserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
FIGURE 13-21:
DS41291D-page 200
SDA
SCL
SEN
BCLIF
S
SSPIF
SDA or SCL are sampled low at the beginning of
the Start condition (Figure 13-21).
SCL is sampled low before SDA is asserted low
(Figure 13-22).
the Start condition is aborted,
and the BCLIF flag is set,
and the MSSP module is reset to its Idle state
(Figure 13-21).
Bus Collision During a Start
Condition
BUS COLLISION DURING START CONDITION (SDA ONLY)
condition if SDA = 1, SCL = 1.
Set SEN, enable Start
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
Set BCLIF,
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SDA = 0, SCL = 1.
Preliminary
SSPIF and BCLIF are
cleared in software.
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 13-23). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0, and during this time, if the SCL pin is
sampled as ‘0’, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
Note:
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
The reason that bus collision is not a factor
during a Start condition, is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus colli-
sion, because the two masters must be
allowed to arbitrate the first address follow-
ing the Start condition. If the address is the
same, arbitration must be allowed to con-
tinue into the data portion, Repeated Start
or Stop conditions.
SSPIF and BCLIF are
cleared in software.
© 2007 Microchip Technology Inc.