RC28F256P30TFB Micron Technology Inc, RC28F256P30TFB Datasheet
RC28F256P30TFB
Specifications of RC28F256P30TFB
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RC28F256P30TFB Summary of contents
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... Password Access feature Software — 25 µs (Typ) program suspend — 25 µs (Typ) erase suspend — Numonyx™ Flash Data Integrator optimized — Basic Command Set and Extended Function Interface (EFI) Command Set compatible — Common Flash Interface capable Density and Packaging — ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR Legal Lines and Disclaimers OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS ...
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P30 - 65 nm Contents 1.0 Functional Description ............................................................................................... 5 1.1 Introduction ....................................................................................................... 5 1.2 Overview ........................................................................................................... 5 1.3 Virtual Chip Enable Description.............................................................................. 6 1.4 Memory Maps ..................................................................................................... 7 2.0 Package Information ................................................................................................. 8 2.1 56-Lead TSOP..................................................................................................... 8 2.2 64-Ball ...
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... AC Write Specifications .......................................................................................59 16.0 Program and Erase Characteristics...........................................................................63 17.0 Ordering Information...............................................................................................64 17.1 Discrete Products...............................................................................................64 17.2 SCSP Products...................................................................................................65 A Supplemental Reference Information.......................................................................66 A.1 Common Flash Interface Tables ...........................................................................66 A.2 Flowcharts ........................................................................................................78 A.3 Write State Machine ...........................................................................................87 B Conventions - Additional Information ......................................................................91 B.1 Conventions......................................................................................................91 B.2 Acronyms .........................................................................................................91 B.3 Nomenclature ...
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... Data is programmed in word increments (16 bits). The P30-65nm protection register allows unique flash device identification that can be used to increase system security. The individual Block Lock34 feature provides zero-latency block locking and unlocking. The P30-65nm device includes enhanced protection via Password Access ...
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Virtual Chip Enable Description The P30-65nm 512-Mbit devices employ a Virtual Chip Enable which combines two 256-Mbit die with a common chip enable, F1-CE# for QUAD+ packages or CE# for Easy BGA packages. Refer to maximum address bit is ...
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P30-65nm 1.4 Memory Maps Figure 1: P30-65nm Memory Map A<24:1 > 256 Mbit (Easy BGA, TSOP) A<23: 0 > 256 Mbit (QUAD+) 64- Kword Block FF 0000 - FFFFFF 64- Kword Block 7F 0000 - 7FFFFF 64- Kword Block 3 ...
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Package Information 2.1 56-Lead TSOP Figure 2: TSOP Mechanical Specifications (256-Mbit) Z See Notes 1 and 3 Pin 1 See Detail A Detail A Table 3: TSOP Package Dimensions (Sheet Product Information Symbol Package Height A ...
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P30-65nm Table 3: TSOP Package Dimensions (Sheet Product Information Symbol Lead Tip Length L Lead Count N Lead Tip Angle θ Seating Plane Coplanarity Y Lead to Package Offset Z Notes: 1. One dimple on package denotes ...
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Easy BGA Package Figure 3: Easy BGA Mechanical Specifications (256-Mbit, 512-Mbit) Ball A1 Corner Top View - Ball side down A1 A2 Table ...
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P30-65nm 2.3 QUAD+ SCSP Packages Figure 4: 88-ball (80 active) QUAD+ SCSP Specifications (256-Mbit, 8x11x1.0 mm Index Mark Top View - Ball Down ...
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Figure 5: 88-ball (80 active) QUAD+ SCSP Specifications (512-Mbit, 8x11x1.2 mm Index Mark Top View - Ball Down A2 Dimensions Package Height ...
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... No Internal Connection on Pin 13; it may be driven or floated. For legacy designs VCC pin and can be tied to Vcc. 4. One dimple on package denotes Pin 1 which will always be in the upper left corner of the package, in reference to the product mark. Datasheet 13 ® Numonyx TM Axcell Flash Memory (P30) 56-Lead TSOP Pinout Top View 56 WAIT 55 A17 54 DQ15 ...
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Figure 7: 64-Ball Easy BGA Ballout (256-Mbit, 512-Mbit VPP B A2 VSS A9 CE A10 A12 A11 RST# E DQ8 DQ1 DQ9 DQ3 F RFU DQ0 ...
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P30-65nm Figure 8: QUAD+ SCSP Ballout and Signals Pin A18 B A5 RFU A17 DQ8 H RFU DQ0 J RFU OE# K F1-CE# ...
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... PPH cycles. VPP can be connected for a cumulative total not to exceed 80 hours. Extended use of this pin may reduce block cycling capability. DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited VCC Power when V ...
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... Flash CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and F1-CE# Input WAIT outputs are placed in high-Z state ...
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... Table 6: QUAD+ SCSP Signal Descriptions (Sheet Symbol Type DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited VCC Power when V CC VCCQ Power OUTPUT POWER SUPPLY: Output-driver source voltage. VSS Power GROUND: Connect to system ground. Do not float any VSS connection. ...
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... Reads To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. 5.2 ...
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... As with any automated device important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory the system boot device CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data ...
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... The on-chip Write State Machine (WSM) manages all block-erase and word-program algorithms. Device commands are written to the Command User Interface (CUI) to control all flash memory device operations. The CUI does not occupy an addressable memory location; ...
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Table 8: Command Codes and Definitions (Sheet Mode Code Device Mode Program or Erase 0xB0 Suspend Suspend 0xD0 Suspend Resume 0x60 Block lock Setup 0x01 Block lock Block Locking/ Unlocking 0xD0 Block Unlock 0x2F Block Lock-Down 0x60 ...
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P30-65nm 6.2 Device Command Bus Cycles Device operations are initiated by writing specific device commands to the Command User Interface (CUI). Several commands are used to modify array data including Word Program and Block Erase commands. Writing either command to ...
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Table 9: Command Bus Cycles (Sheet Mode Command Blank Check Block Blank Check Extended Function Interface EFI (5) command Notes: 1. First command cycle address should be the same as the operation’s target address. DBA = Device ...
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... AVQV In asynchronous page mode, sixteen data words are “sensed” simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on the Address bus is driven onto DQ[15:0] after the initial access delay. The lowest four address bits determine which word of the 16- word page is output from the data buffer at any given time ...
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... The 512-Mbit devices do not have a unique Device ID associated with them. Each die within the stack can be identified by either of the 256-Mbit Device ID codes depending on its parameter option. 7.4 Read CFI The Read CFI command instructs the device to output Common Flash Interface (CFI) data when read. See Read CFI command. CFI information and address offsets within the CFI database. ...
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... The device features a 512-word buffer to enable optimum programming performance. For Buffered Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. ...
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... After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set ...
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... BEFP programs one block at a time; all buffer data must fall within a single block Suspend BEFP cannot be suspended Programming the flash Programming to the flash memory array can occur only when the buffer is full. memory array Note: 1. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly ...
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... During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 512, the remaining buffer locations must be filled with 0xFFFF ...
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P30-65nm 8.4 Program Suspend Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from the device other than the one being programmed. The Program Suspend command can be issued to any device ...
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Figure 11: Example VPP Supply Connections ≤ 10K Ω • Factory Programming with • Complete write/Erase Protection when PPH • Low Voltage and Factory Programming Datasheet 32 V VCC CC PROT ...
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... P30-65nm 9.0 Erase Operations Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail. ...
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The status register can be examined for Blank Check progress and errors by reading any address within the block being accessed. During a blank check operation, the Status Register indicates a busy status (SR.7 = 0). Upon completion, the Status ...
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... The following sections describe each security mode in detail. 10.1 Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power- locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. ...
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Figure 12: Block Locking State Diagram Note: LK: ...
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P30-65nm 10.2 Selectable One-Time Programmable Blocks The OTP security feature on P30-65nm device is backward compatible to the P30- 130nm device. Please see your local Numonyx representative for details about its implementation. 10.3 Password Access The Password Access is a ...
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Registers When non-array reads are performed in asynchronous page mode only the first data is valid and all subsequent data are undefined. When a non-array read operation occurs as synchronous burst mode, the same word of data requested will ...
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P30-65nm Table 14: Status Register Description (Sheet Status Register (SR) Program Suspend Status 2 (PSS) 1 Block-Locked Status (BLS) 0 BEFP Status (BWS) Note: Always clear the Status Register prior to resuming erase operations. It avoids Status ...
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Table 15: Read Configuration Register Description (Sheet 14:11 Latency Count (LC[3:0]) WAIT Polarity (WP Reserved (R) 8 WAIT Delay (WD) Burst Sequence (BS) 7 Clock Edge (CE) 6 5:4 Reserved (R) Burst Wrap (BW) 3 ...
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P30-65nm Figure 13: First-Access Latency Count CLK [C] Valid Address [A] Address ADV# [V] Code 0 (Reserved) DQ [D/Q] Output 15-0 Code 1 (Reserved DQ [D/Q] 15-0 Code 2 DQ [D/Q] 15-0 Code 3 DQ [D/Q] 15-0 Code 4 DQ ...
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Table 16: LC and Frequency Support Latency Count Settings 5 (TSOP); 4 (Easy BGA) 5 (Easy BGA) Figure 14: Example Latency Count Setting using Code 3 CLK CE# ADV# A[MAX:0] A[MAX:1] D[15:0] 11.2.3 End of Word Line (EOWL) Considerations End ...
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P30-65nm Table 17: End of Wordline Data and WAIT state Comparison Latency Count Data States 1 Not Supported Not Supported ...
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Table 18: WAIT Functionality Table Condition CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’ CE# =’0’, OE# = ‘0’ Synchronous Array Reads Synchronous Non-Array Reads All Asynchronous Reads All Writes Notes: 1. Active: WAIT is ...
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... Burst Length The Burst Length bits (BL[2:0]) select the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word or continuous. Continuous-burst accesses are linear only, and do not wrap within any word length ...
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Users can program these registers as needed. Once programmed, users can then lock the OTP Register(s) to prevent additional bit programming (see “OTP Register Map” on page The OTP Registers contain one-time programmable (OTP) bits; when programmed, PR ...
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P30-65nm perform a read operation using the address offset corresponding to the register to be read. Table 10, “Device Identifier Information” on page 26 the OTP Registers and Lock Registers. PR data is read 16 bits at a time. 11.3.2 ...
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... Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected ...
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... Two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. Because flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. High-frequency, inherently low-inductance capacitors should be placed as close as possible to package leads ...
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Maximum Ratings and Operating Conditions 13.1 Absolute Maximum Ratings Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Table 21: Parameter Temperature under bias Storage temperature Voltage on any signal ...
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P30-65nm 14.0 Electrical Specifications 14.1 DC Current Characteristics Table 23: DC Current Characteristics (Sheet Sym Parameter I Input Load Current LI Output I Leakage DQ[15:0], WAIT LO Current 256-Mbit Standby, CCS CC I Power-Down ...
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Table 23: DC Current Characteristics (Sheet Sym Parameter I V Blank Check PPBC PP Notes: 1. All currents are RMS unless noted. Typical values at typical the average current measured over any 5 ...
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P30-65nm 15.0 AC Characteristics 15.1 AC Test Conditions Figure 18: AC Input/Output Reference Waveform V CCQ Input V /2 CCQ 0V Note: AC test inputs are driven at V CCQ and fall times (10% to 90%) < 5 ns. Worst ...
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Capacitance Table 26: Capacitance Parameter Signals Address, Data, Input CE#, WE#, OE#, Capacitance RST#, CLK, ADV#, WP# Output Data, WAIT Capacitance Notes: 1. Sampled, but not 100% tested. 15.3 AC Read Specifications Table 27: AC Read Specifications (Sheet 1 ...
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P30-65nm Table 27: AC Read Specifications (Sheet Num Symbol R101 t Address setup to ADV# high AVVH R102 t CE# low to ADV# high ELVH R103 t ADV# low to output valid VLQV R104 t ADV# pulse ...
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Figure 21: Asynchronous Single-Word Read (ADV# Low) Address [A] ADV# CE# [E} OE# [G] R15 WAIT [ Data [D/Q] RST# [P] Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low). Figure 22: Asynchronous Single-Word Read ...
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... WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst. Datasheet ...
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Figure 25: Continuous Burst Read, Showing An Output Delay Timing R301 R302 R306 CLK [C] R2 R101 Address [A] R106 R105 R105 ADV# [V] R303 R102 R3 CE# [E] OE# [G] R15 WAIT [T] R7 Data [D/Q] Notes: 1. WAIT ...
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P30-65nm 15.4 AC Write Specifications Table 28: AC Write Specifications Num Symbol W1 t RST# high recovery to WE# low PHWL W2 t CE# setup to WE# low ELWL W3 t WE# write pulse width low WLWH W4 t Data ...
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Figure 27: Write-to-Write Timing W5 Address [A] W2 CE# [E} WE# [W] OE# [G] Data [D/Q] W1 RST# [P] Figure 28: Asynchronous Read-to-Write Timing R2 Address [A] R3 CE# [E} OE# [G] WE# [W] WAIT [ Data [D/Q] ...
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P30-65nm Figure 29: Write-to-Asynchronous Read Timing W5 Address [A] ADV# [V] W2 CE# [ WE# [W] OE# [G] WAIT [T] Data [D/Q] W1 RST# [P] Figure 30: Synchronous Read-to-Write Timing R301 R302 R306 CLK [C] R2 R101 Address ...
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Figure 31: Write-to-Synchronous Read Timing CLK W5 Address [A] ADV# W2 CE# [ WE# [W] OE# [G] WAIT [T] W4 Data [D/Q] W1 RST# [P] Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.10=0, ...
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P30-65nm 16.0 Program and Erase Characteristics Table 29: Program and Erase Specifications Num Symbol Parameter Program W200 t Single word PROG/W Time Aligned 32-Word, BP time (32 words) Aligned 64-Wd, BP time (64 words) Program Aligned 128-Wd, BP time W250 ...
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... Package Designator -Lead TSOP, lead-free RC = 64- Ball Easy BGA , leaded Ball Easy BGA, lead-free Product Line Designator 28F = Numonyx™ Flash Memory Device Density 256 = 256- Mbit Note: The last digit is randomly assigned to cover packing media and/or features or other specific configuration ...
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... Figure 33: Decoder for SCSP P30-65nm Package Designator RD = Numonyx™ SCSP, leaded PF = Numonyx™ SCSP, lead - free RC = 64- Ball Easy BGA , leaded PC = 64- Ball Easy BGA, lead - free Product Designator 48F = Numonyx™ Flash Memory Only Device Density die 4 = 256-Mbit Product Family ® Numonyx Axcell ...
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... The system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. ...
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... A.1.2 CFI Structure Overview The CFI command causes the flash component to display the Common Flash Interface (CFI) structure or “database.” The structure sub-sections and address locations are summarized below. Table 34: CFI Structure 00001-Fh Reserved 00010h CFI query identification string ...
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Table 35: CFI Identification Offset Length 10h 3 Query-unique ASCII string “QRY“ 13h 2 Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms 15h 2 Extended Query Table primary algorithm address 17h 2 Alternate ...
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P30-65nm A.1.4 Device Geometry Definition Table 36: System Interface Information Offset Length VCC logic supply minimum program/erase voltage 1Bh 1 VCC logic supply maximum program/erase voltage 1Ch 1 VPP [programming] supply minimum program/erase voltage 1Dh 1 VPP [programming] supply maximum ...
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... Table 37: Device Geometry Definition Offset Length 27h 1 “n” such that device size = 2 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device w idth capabilities as described in the table 28h 2 — — — — ...
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... Instant individual block locking supported bit 6 Protection bits supported bit 7 Pagemode read supported bit 8 Synchronous read supported bit 9 Simultaneous operations supported bit 10 Extended Flash Array Blocks supported bit 30 CFI Link(s) to follow bit 31 Another "Optional Features" field to follow (P+9)h 1 Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1– ...
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... Datasheet 72 Description (Optional flash features and com m ands) n =factory pre-programmed bytes n =user programmable bytes n = user programmable bytes/group P30-65nm Hex Add ...
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... Datasheet 73 Description (Optional flash features and commands) n HEX value represents the number of n+1 HEX value represents the maximum number of Description (Optional flash features and commands) Hex Add. Code Value 127: --05 32 byte 128: --04 4 129: --01 ...
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... Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) +(Type 2 blocks)x(Type 2 block sizes)+...+(Type n blocks)x(Type n block sizes) Datasheet 74 Description (Optional flash features and com m ands) P30-65nm See table below Address Len Bot Top 2 ...
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... Reserved (P+38)h (P+38)h bits 32- Control Mode invalid size in bytes (P+39)h (P+39)h bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32) (P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information (P+3B)h (P+3B)h bits 0– y identical-size erase blks in a partition (P+3C)h (P+3C)h bits 16– ...
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Table 43: Partition and Erase Block Region Information Partition and Erase-block Region Information Address 12D: 12E: 12F: 130: 131: 132: 133: 134: 135: 136: 137: 138: 139: 13A 13B: 13C: 13D: 13E: 13F: 140: 141: 142: 143: 144: 145: 146: ...
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P30-65nm Table 44: CFI Link Information Offse t ( 10Ah (P+48)h 4 CFI Link Field bit definitions (P+49)h Bits 0–9 = Address offset (w ithin 32Mbit segment) of referenced CFI table (P+4A)h Bits 10–27 = nth ...
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A.2 Flowcharts Figure 35: Word Program Flowchart Start Command Cycle - Issue Program Command - Address = location to program - Data = 0x40 Data Cycle - Address = location to program - Data = Data to program Check Ready ...
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P30-65nm Figure 36: Program Suspend/Resume Flowchart Start Read Status Write 70h Any Address Program Suspend Write B0h Any Address Read Status Register Read Array Write FFh Any Address Read Array ...
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... Count ranges for this device are N=0000h to 00FFh. 2. The device outputs the status register when read. 3. Write Buffer contents will be programmed at the device start address or destination flash address . Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A Write Buffer Data 5 ...
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P30-65nm Figure 38: BEFP Flowchart Setup Phase Start Issue BEFP Setup Cmd (Data = 0x80) Issue BEFP Confirm Cmd (Data = 00D0h) BEFP Setup Delay Read Status Register Yes (SR.7=0) BEFP Setup Done ? No (SR.7=1) SR Error Handler (User-Defined) ...
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Figure 39: Block Erase Flowchart Start Command Cycle - Issue Erase command - Address = Block to be erased - Data = 0x20 Confirm Cycle - Issue Confirm command - Address = Block to be erased - Data = Erase ...
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P30-65nm Figure 40: Erase Suspend/Resume Flowchart Start Read Status Write 70h Any Address Erase Suspend Write B0h Any Address Read Status Register Read Program Read or Program? Read Array No ...
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Figure 41: Block Lock Operations Flowchart Start Lock Setup Write 60 h Block Address Lock Confirm Write 01 ,D0,2Fh Block Address Read ID Plane Write 90 h Read Block Lock Status Locking No Change ? Yes Read Array Write FFh ...
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P30-65nm Figure 42: Protection Register Programming Flowchart Datasheet 85 Start OTP Program Setup - Write 0xC0 - OTP Address Confirm Data - Write OTP Address and Data Check Ready Status - Read Status Register Command not required - Perform read ...
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Figure 43: Status Register Flowchart - Issue Status Register Command - Address = any device address - Data = 0x70 - Read Status Register SR[7:0] - Set/Reset by WSM - Set by WSM - Reset by user - See Clear ...
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P30-65nm A.3 Write State Machine The Next State Table shows the command state transitions (Next State Table) based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read ...
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Table 45: Next State Table for P30-65nm (Sheet Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) Setup (8) BP Load 1 (8) BP Load 2 BP Confirm Ready (Error [Botch]) Buffer Pgm ...
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P30-65nm Table 45: Next State Table for P30-65nm (Sheet Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) EFI Setup Sub-function Setup Sub-op-code Load 1 Sub-function Sub-function Confirm in Erase Suspend if data load in ...
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Table 46: Output Next State Table for P30-65nm Current Chip State (FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h) BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP Setup, Load 1, Load 2 BP Setup, ...
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... Mbit: 1,048,576 bits MByte: 1,048,576 bytes MWord: 1,048,576 words B.2 Acronyms BEFP: Buffer Enhanced Factory Programming CFI: Common Flash Interface MLC: Multi-Level Cell OTP: One-Time Programmable PLR: Protection Lock Register PR: Protection Register RCR: Read Configuration Register RFU: Reserved for Future Use ...
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... Bottom parameter device : Datasheet 92 A group of bits, bytes, or words within the flash memory array that erase simultaneously. The P30-65nm has two block sizes: 32 KByte and 128 KByte. An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks. ...
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... Table 23, “DC Current Characteristics” on page 51 Correct VHH PPH note 7. Remove 128M related contents; Return to StrataFlash trademark; Update the buffer program for cross 512-Word boundary; Correct A24 to A25 for virtual CE description in section 1.3; Remove Numonyx Confidential. Update Buffer program flowchart same as 130nm; Minor wording modifications. ...
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Revision Date Revision May 2008 01 Datasheet 94 Description Initial Release P30-65nm Mar 2010 Order Number: 320002-10 ...