RC28F256P30TFB Micron Technology Inc, RC28F256P30TFB Datasheet - Page 29

• Manufacturer Part Number: RC28F256P30TFB
• Manufacturer: Micron Technology Inc

Specifications of RC28F256P30TFB

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 100ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

P30-65nm
8.3.1
Table 12: BEFP Requirements
Note:
Table 13: BEFP Considerations
Note:
1.
2.
3.
8.3.2
Datasheet
29
Case Temperature
V
VPP
Setup and Confirm
Programming
Buffer Alignment
Cycling
Programming blocks
Suspend
Programming the flash
memory array
CC
Parameter/Issue
Parameter/Issue
Word buffer boundaries in the array are determined by A[9:1] for Easy BGA and TSOP, A[8:0] for QUAD+ package (0x000
through 0x1FF). The alignment start point is A[9:1] = 0x000 for Easy BGA and TSOP, A[8:0] = 0x000 for QUAD+ package.
Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work
properly.
If the internal address counter increments beyond the block's maximum address, addressing wraps around to the
beginning of the block.
If the number of words is less than 512, remaining locations must be filled with 0xFFFF.
A single two-cycle command sequence programs the entire block of data. This
enhancement eliminates three write cycles per buffer: two commands and the word
count for each set of 512 data words. Host programmer bus cycles fill the device’s write
buffer followed by a status check. SR.0 indicates when data from the buffer has been
programmed into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the Write State Machine
(WSM) increments internal addressing to automatically select the next 512-word array
boundary. This aspect of BEFP saves host programming equipment the address-bus
setup overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
BEFP Requirements and Considerations
BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit
SR.7 (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A
delay before checking SR.7 is required to allow the WSM enough time to perform all of
T
Nominal Vcc
Driven to V
Target block must be unlocked before issuing the BEFP Setup and Confirm commands
The first-word address (WA0) of the block to be programmed must be held constant
from the setup phase through all data streaming into the target block, until transition
to the exit phase is desired
WA0 must align with the start of an array buffer boundary
For optimum performance, cycling must be limited below 50 erase cycles per block.
BEFP programs one block at a time; all buffer data must fall within a single block
BEFP cannot be suspended
Programming to the flash memory array can occur only when the buffer is full.
C
= 30
°
C ± 10 °C
PPH
Requirement
Requirement
Order Number: 320002-10
1
1
2
3
Notes
Notes
Mar 2010