RC28F256P30TFB Micron Technology Inc, RC28F256P30TFB Datasheet - Page 24

• Manufacturer Part Number: RC28F256P30TFB
• Manufacturer: Micron Technology Inc

Specifications of RC28F256P30TFB

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 100ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Table 9:
Datasheet
24
Notes:
1.
2.
3.
4.
5.
Blank Check
Mode
EFI
First command cycle address should be the same as the operation’s target address.
DBA = Device Base Address (NOTE: needed for dual-die 512 Mb device)
DnA = Address within the device.
IA = Identification code address offset.
CFI-A = Read CFI address offset.
WA = Word address of memory location to be written.
BA = Address within the block.
OTP-RA = Protection Register address.
LRA = Lock Register address.
RCD = Read Configuration Register data on A[16:1] for Easy BGA and TSOP, A[15:0] for QUAD+ package.
ID = Identifier data.
CFI-D = CFI data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
OTP-D = Protection Register data.
LRD = Lock Register data.
The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This
is followed by up to 512 words of data. Then the confirm command (0xD0) is issued, triggering the array programming
operation.
The confirm command (0xD0) is followed by the buffer data.
The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1≤ N ≤ 512. The subsequent cycles load data
words into the program buffer at a specified address until word count is achieved, after the data words are loaded, the
final cycle is the confirm cycle 0xD0).
Command Bus Cycles (Sheet 2 of 2)
Block Blank Check
Extended Function Interface
command
Command
(5)
Cycles
Bus
>2
2
Oper
Write
Write
First Bus Cycle
Addr
WA
BA
(1)
Data
0xBC
0xEB
(2)
Oper
Write
Write
Second Bus Cycle
Order Number: 320002-10
Addr
WA
BA
(1)
P30-65nm
Data
Sub-Op
Mar 2010
code
D0
(2)