RC28F256P30TFB Micron Technology Inc, RC28F256P30TFB Datasheet - Page 80

• Manufacturer Part Number: RC28F256P30TFB
• Manufacturer: Micron Technology Inc

Specifications of RC28F256P30TFB

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 100ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Figure 37: Buffer Program Flowchart
Datasheet
80
Yes
Command E8h and
Read Status Register
Read Status Register
Write Confirm D0h
Another Buffered
Issue Write to Buffer
Write Word Count
and Block Address
Write Buffer Data
Program Complete
Is WSM Ready ?
Block Address
Check if Desired
Programming?
Supports Buffer
Target Address
Block Address
Block Address
Set Timeout or
Loop Counter
Start Address
Full Status
X = N?
Get Next
SR. 7 =?
(note 7)
SR. 7 =
Writes ?
Device
X = 0
Start
1
1 = Yes
Yes
Yes
No
No
No
Write Buffer Data
Buffered Program
Use Single Word
Block Address
Abort Bufferred
Write to another
Block Address
Programming
Program?
X = X + 1
No
Expired?
Timeout
or Count
Aborted
Suspend
Program
No
Yes
No
Yes
Yes
Suspend
Program
Loop
Notes:
1. Word count values on DQ
register. Count ranges for this device are N=0000h to 00FFh.
2. The device outputs the status register when read.
3. Write Buffer contents will be programmed at the device start
address or destination flash address .
4. Align the start address on a Write Buffer boundary for maximum
programming performance (i.e., A
5. The device aborts the Buffered Program command if the
current address is outside the original block address .
6. The Status register indicates an “improper command
Sequence” if the Buffered Program command is aborted. Follow
this with a Clear Status Register command .
7. The device default state is to output SR data after the Buffered
Programming Setup Command (E8h).CE# and OE low drive the
device to update Status Register . It is not allowed to issue 70h to
read SR data after E8h command otherwise 70h would be
counted as Word count.
8. Full status check can be done after all erase and write
sequences complete . Write FFh after the last operation to reset
the device to read array mode.
( Notes 1, 2)
( Notes 3, 4)
( Notes 5, 6)
Operation
Standby
Standby
(Note 7)
Read
Bus
Write
Write
Write
Write
Write
Read
Command
Confirm
Program
Write to
Buffer
.
0
-DQ
SR. 7 = Valid
1 = Device WSM is Busy
0 = Device WSM is Ready
Status register Data
CE # and OE# low updates SR
1 = WSM Ready
N = 0 corresponds to count = 1
0 = WSM Busy
Data = E8H
Addr = Block Address
Addr = Block Address
Check SR .7
Data = N- 1 = Word Count
Addr = Block Address
Data = Write Buffer Data
Addr = Start Address
Data = Write Buffer Data
Addr = Block Address
Data = D0H
Addr = Block Address
Addr = Block Address
Check SR .7
15
8
-A
are loaded into the Count
1
of the start address =0).
Order Number: 320002-10
Comments
.
P30-65nm
.
Mar 2010