RC28F256P30TFB Micron Technology Inc, RC28F256P30TFB Datasheet - Page 39

• Manufacturer Part Number: RC28F256P30TFB
• Manufacturer: Micron Technology Inc

Specifications of RC28F256P30TFB

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 100ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

P30-65nm
Table 14: Status Register Description (Sheet 2 of 2)
Note:
11.1.1
11.2
Table 15: Read Configuration Register Description (Sheet 1 of 2)
Datasheet
39
Status Register (SR)
Read Configuration Register (RCR)
15
Mode
Read
RM
Bit
15
2
1
0
ambiguity when issuing commands during Erase Suspend. If a command sequence error
occurs during an erase-suspend state, the Status Register contains the command sequence
error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible errors
during the erase operation cannot be detected via the Status Register because it contains the
previous error status.
Always clear the Status Register prior to resuming erase operations. It avoids Status Register
Read Mode (RM)
14
Program Suspend Status
(PSS)
Block-Locked Status (BLS)
BEFP Status (BWS)
Latency Count
Clear Status Register
The Clear Status Register command clears the status register. It functions independent
of V
SR[5:3,1] without clearing them. The Status Register should be cleared before starting
a command sequence to avoid any ambiguity. A device reset also clears the Status
Register.
Read Configuration Register
The RCR is a 16-bit read/write register used to select bus-read mode (synchronous or
asynchronous), and to configure synchronous burst read characteristics of the device.
To modify RCR settings, use the Configure Read Configuration Register command (see
Section 6.0, “Command Set” on page
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (see
page
Upon power-up or exit from reset, the RCR defaults to asynchronous mode.
The following sections describe each RCR bit.
13
LC[3:0]
Name
PP
. The Write State Machine (WSM) sets and clears SR[7,6,2], but it sets bits
48).
12
11
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
Polarity
WAIT
WP
10
0 = Program suspend not in effect.
1 = Program suspend in effect.
0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
After Buffered Enhanced Factory Programming (BEFP) data is loaded into the
buffer:
0 = BEFP complete.
1 = BEFP in-progress.
RES
R
9
Section 12.0, “Power and Reset Specifications” on
Delay
WAIT
WD
8
21).
Burst
Seq
BS
7
Edge
CLK
CE
6
Description
RES
R
5
RES
R
4
Burst
Wrap
BW
3
Order Number: 320002-10
Default Value = 0x80
2
Burst Length
BL[2:0]
1
Mar 2010
0