RC28F256P30TFB Micron Technology Inc, RC28F256P30TFB Datasheet - Page 38

• Manufacturer Part Number: RC28F256P30TFB
• Manufacturer: Micron Technology Inc

Specifications of RC28F256P30TFB

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 100ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

11.0
11.1
Table 14: Status Register Description (Sheet 1 of 2)
Datasheet
38
Status Register (SR)
Device Write
Status
DWS
Bit
7
7
6
5
4
3
Device Ready Status (DWS)
Erase Suspend Status (ESS)
Erase Status
(ES)
Program
Status (PS)
V
Erase Suspend
Registers
When non-array reads are performed in asynchronous page mode only the first data is
valid and all subsequent data are undefined. When a non-array read operation occurs
as synchronous burst mode, the same word of data requested will be output on
successive clock edges until the burst length requirements are satisfied.
Read Status Register
To read the Status Register, issue the Read Status Register command at any address.
Status Register information is available to which the Read Status Register, Word
Program, or Block Erase command was issued. Status Register data is automatically
made available following a Word Program, Block Erase, or Block Lock command
sequence. Reads from the device after any of these command sequences outputs the
device’s status until another valid command is written (e.g. Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. Status Register data is output on DQ[7:0], while 0x00 is output on
DQ[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs
first) updates and latches the Status Register contents. However, reading the Status
Register in synchronous burst mode, CE# or ADV# must be toggled to update status
data.
The Device Write Status bit (SR.7) provides overall status of the device. Status register
bits SR[6:1] present status and error information about the program, erase, suspend,
V
PP
PP
Status (VPPS)
Status
, and block-locked operations.
ESS
6
Name
Erase Status
Command
Sequence
Error
ES
5
0 = Device is busy; program or erase cycle in progress; SR.0 valid.
1 = Device is ready; SR[6:1] are valid.
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
SR.5
0 = VPP within acceptable limits during program or erase operation.
1 = VPP
0
0
1
1
Program
Status
PS
4
SR.4
≤
0
1
0
1
VPPLK during program or erase operation.
Description
Program or Erase operation successful.
Program error - operation aborted.
Erase error - operation aborted.
Command sequence error - command aborted.
V
PP
VPPS
Status
3
Description
Suspend
Program
Status
PSS
2
Block-Locked
Status
Order Number: 320002-10
BLS
1
Default Value = 0x80
P30-65nm
Status
BEFP
BWS
Mar 2010
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